Update on STM
morepypy.blogspot.comObligatory anti STM hype links:
http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...
Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.
Is there any plans to work hardware transactional memory into the mix?
Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
Even new Intel Haswell's STM?
Yes, Intel TSX too has a limited transaction size.