A permissively licensed Vita FPGA Architecture in only 380 lines of Verilog

The Vita FPGA Architecture Verilog files VitaFPGAArchLogicBlock.v and VitaFPGAArchMemoryBlock.v are bugfree.

Using two input, one output nand or two input, one output nor gates, one can express any possible truth table.

The VitaFPGAArchMemoryBlock.v file implements a D-Flip Flop with two configurable inputs and two configurable outputs that output the same value in two directions.

The VitaFPGAArchLogicBlock.v file implements a LUT2 with two configurable inputs and two outputs outputting one bit in two directions.

A LUT2 can be programmed to ignore one or both inputs.

Thus, any possible truth table can be expressed with enough Vita FPGA Architecture Logic Blocks.