MESI Cache Coherency Protocol Visualization

Obviously cache snooping is going to be device-dependent, but the way this shows things happening is that if you write an address that exists in another CPU's cache, that the invalidation doesn't happen until that CPU later tries to read the address. That requires two snoop cycles be dedicated, which is a waste. The secondary CPU is already listening to the snoop bus, it can/should (and in practice does on basically all devices, AFAIK) be able to recognize that write fly by and free up its cache line preemptively.

This is awesome! It's a great aid in understanding the protocol.