saigovardhan
- Karma
- 107
- Created
- 2 years ago
About
CPU uArch Design Engineerhttps://govardhnn.github.io/
Recent Submissions
- 1. ▲ A Compelling Case for Using BSV (Bluespec SystemVerilog) in Academia (incoresemi.com)
- 2. ▲ A Compelling Case for Using Bluespec SystemVerilog in Academia (incoresemi.com)
- 3. ▲ 5G networks meet consumer needs as mobile data growth slows (spectrum.ieee.org)