GitHub stars on public, non-fork chip design repositories, by company. Data collected October 11, 2026.
Where do you think AI would be today if it weren’t for 40+ years of tireless contributions from open science and open source heroes?
…the answer is nowhere!
Very few of those open source heroes will ever get a proper monetary reward for their contributions, but that’s OK because they all did it for a higher purpose (right??). We know some of these heroes by name (Torvalds, Stallman, Thompson/Ritchie, van Rossum, Lattner) but sometimes we forget the corporate contributions that helped turn prototypes into products. Linux wouldn’t be Linux without the billions of dollars spent by Intel, NVIDIA, Samsung, and AMD. TensorFlow and PyTorch wouldn’t exist without Facebook and Google.
The semiconductor industry that controls the AI pipeline is a trillion-dollar economy run by a handful of players whose open source chip design contribution is essentially $0. Sadly the world of chip design is still stuck in the mindset that “Only the paranoid survive” (Andy Grove), “Linux is a cancer” (Steve Ballmer), and “you can take my IP from my cold dead hands” (unknown). From a business perspective, keeping everything siloed and proprietary makes sense, but personally I think it’s a moral imperative to open source anything that doesn’t hurt our ability to make a living.
At Zero ASIC open sourcing non-critical IP is one of our core operating principles and we have contributed millions of dollars in development to open source infrastructure projects over the last five years. When I started the IDEA and POSH programs at DARPA in 2017, the transition plan for projects like OpenROAD and OpenFPGA was for big chip companies to start contributing resources and funding to development projects out of their own interest but apart from Zero ASIC and a couple of other outliers this never happened. Imagine where OpenROAD and Yosys would be today if everyone would properly pitch in!
To give you an idea of how Zero ASIC has contributed to open source over the years and how little the semiconductor industry contributes, I decided to run an experiment on GitHub using stars as a metric. I am kind of proud that Zero ASIC turned out to rank #1 in the world! That means that Zero ASIC (with ~10 people and a market cap of ~$0M) has arguably contributed more to open source hardware than every single chip giant with a trillion-dollar market cap.
Of course, “the dream” is for Zero ASIC to grow up and one day join the trillion-dollar club. If we do, I can guarantee you that we won’t forget our mission. If you believe in Zero ASIC’s mission to democratize silicon and want to help out in any way, DM me.
We queried public GitHub organizations to tally the star count for large organizations as well as startups. It was by no means a rigorous academic study, but it was illuminating nonetheless.
Chip design stars divided by approximate headcount. See “How we counted” below for headcount sources.
| Company | Chip design stars | Employees (approx.) | Stars per employee |
|---|---|---|---|
| Zero ASIC | 3,949 | 10 | 395 |
| SiFive | 1,949 | 500 | 3.9 |
| Tenstorrent | 196 | 1,000 | 0.20 |
| Analog Devices | 2,144 | 24,000 | 0.09 |
| NVIDIA | 3,376 | 42,000 | 0.08 |
| AMD | 2,294 | 31,000 | 0.07 |
| Intel | 1,723 | 85,100 | 0.02 |
That is about 100 times more than the next company and about 4,900 times more than NVIDIA.
We also checked the 320 companies in the list of Awesome Semiconductor Startups. These are the smaller startups with open source chip design work on GitHub:
| Startup | Chip design stars | Highlights |
|---|---|---|
| Bluespec | 2,195 | BSC compiler (1,144), Flute, Piccolo, and Toooba RISC-V cores |
| getinstachip | 165 | vpm, a Verilog package manager |
| Semify | 59 | Waveform and verification tools |
| Ingonyama | 52 | open-binius, Verilog building blocks for ZK proofs |
| ChipFlow | 51 | vajax SPICE simulator, chipflow-lib, example SoCs |
| Riverlane | 37 | qeciphy, an FPGA-to-FPGA physical layer |
| Silimate | 24 | EDA utilities |
| zeroRISC | 12 | expo |
| Rivos | 11 | JumpStart, a RISC-V CPU and SoC validation framework |
Bluespec stands out. It open sourced its BSC compiler and publishes a family of RISC-V cores, and it would rank fourth in the chart at the top, just behind AMD. After Bluespec the numbers drop quickly. Most of the startup list has no chip design repositories at all, including well-funded AI chip companies such as Groq, Etched, SambaNova, d-Matrix, Lightmatter, Ayar Labs, Axelera, SiMa.ai, Rebellions, and Furiosa, whose public repositories are SDKs, model zoos, and inference examples.
Where our stars come from
The Zero ASIC count includes the work of our team going back to Adapteva and Parallella:
- OH!, a Verilog library for ASIC and FPGA designers (1,442)
- SiliconCompiler, a modular hardware build system (1,230)
- Switchboard, a communication framework for RTL simulation and emulation (324)
- UMI, the Universal Memory Interface (170)
- Wildebeest, an FPGA synthesis tool (146)
- LambdaPDK, a library of open PDK packages (134)
- LogikBench, a digital logic benchmark suite (89)
- SiliconCompiler Gallery, a design gallery for SiliconCompiler (79)
- Logik, a configurable RTL to bitstream FPGA toolchain (64)
- ZeroSoC, a demo SoC for SiliconCompiler (63)
- OpenEDA, an open source EDA chip design flow (53)
- Lambdalib, a modular hardware abstraction library (53)
- Logiklib, a library of FPGA architectures (33)
- EBRICK demo, how to create a custom EBRICK (30)
- Epiphany DV archive, the Epiphany design verification infrastructure (13)
- Seven smaller repositories with fewer than 10 stars each (26)
How we counted
- Companies: 25 semiconductor companies, from the largest (NVIDIA, Intel, AMD, Qualcomm, Broadcom) to startups (SiFive, Tenstorrent, Cerebras, SambaNova, Hailo). Each company includes all of its GitHub organizations we could find; for example, NVIDIA includes NVIDIA, NVlabs, and NVDLA, and AMD includes AMD, Xilinx, and ROCm. Zero ASIC includes zeroasiccorp, siliconcompiler, parallella, adapteva, and aolofsson/oh.
- Repositories: public repositories only, forks excluded, stars as reported by the GitHub API on October 11, 2026.
- Chip design: only repositories for designing chips count: RTL, HLS to RTL, EDA tools and PDKs, and hardware testbenches. We started with every repository whose primary language is Verilog, SystemVerilog, VHDL, or Bluespec, or whose name, description, or topics refer to RTL, FPGA, ASIC, EDA, HLS, synthesis, PDKs, and similar, and then reviewed the list by hand. Software that runs on chips (SDKs, drivers, runtimes, firmware, operating systems, AI frameworks) is not counted, nor are vendor SDKs that only target the vendor’s own architecture, such as AMD Vitis, FINN, and RapidWright, and neither are board and PCB design files, documentation, or virtual platforms. 121 of the 7,495 starred repositories met the bar.
- Headcount: from the most recent annual reports where available, and public estimates otherwise. Zero ASIC is counted as its ten current full-time engineers. The ranking per employee does not change under any reasonable choice of headcount.
- Startups: we matched the 320 startups in the Awesome Semiconductor Startups list to GitHub organizations by website domain or exact name and found organizations for 200 of them, then applied the same chip design rules. Bluespec’s count includes the B-Lang-org organization, where its BSC compiler is maintained. Startups that publish under personal accounts or unrelated organization names would be missed.
- Not chip companies: two companies doing substantial open source chip design work are not in the comparison because they do not sell chips. Precision Innovations leads development of OpenROAD, the open source RTL-to-GDS flow, which has about 4,000 stars across the repositories it leads. Antmicro, an engineering services company, has about 800 stars on chip design repositories in its own organization and is a major contributor to Verilator, F4PGA, and other projects hosted elsewhere. We are grateful for both.
Organizations we missed would raise some numbers. If you know of one, let us know and we will add corrections to this post.