By pushing into a new dimension, engineers at IBM have nearly doubled the number of transistors they can fit on a microchip—the sort of device that animates your computer—cramming nearly 100 billion of them into a square centimeter. Announced yesterday, the advance continues a historic but slowing trend known as Moore’s Law that since the 1960s has seen the number of transistors on a chip double roughly every 2 years. But it underscores how engineers can no longer simply shrink transistors. To realize the increase, IBM researchers stacked them.
“For the first time in history, we enable the scaling of transistors in the vertical direction,” says Huiming Bu, an electrical engineer and IBM’s vice president for global semiconductor R&D. James Rondinelli, a materials scientist at Northwestern University who was not involved with the work, says, “It’s another step jump. You’re going to see all of the other semiconductor companies adopt this approach” to chip design. IBM does not make chips itself, but rather licenses its technologies.
IBM says the chip has reached the 0.7-nanometer “node,” making it the first subnanometer chip. In fact, the smallest features on the new chip are about 14 to 20 nanometers wide, the same as the current state of the art, but the design of the transistors enables them to be packed far more tightly.
A transistor is a switch in which a thin channel of a semiconductor connects one metallic electrode called the source to another called the drain. A third electrode called the gate crosses the channel, separated from it by a thin layer of insulator. Controlling the gate voltage either allows current to flow from source to drain or stops the flow. Billions of transistors interconnect on a single chip to produce the microprocessors and memory chips that power everything from cellphones to data centers for artificial intelligence (AI).
To make chips, manufacturers first lay down layers of the requisite materials on a silicon wafer and cover everything with a light-sensitive material known as a photoresist. A pattern of light is projected onto the wafer to trace the circuits. Removing only the light-exposed photoresist allows the underlying material to be etched away to form the circuits.
For decades, chip design was a 2D affair, with the gate simply lying across the channel, and the quoted size scale had a physical meaning. “Back then, that number meant the length of the channel,” says Chang-Yong Nam, a materials scientist at Brookhaven National Laboratory who was not involved with the new work. Shorter was better, and engineers made transistors smaller by patterning a chip with light of ever-shorter wavelengths.
A decade ago, researchers dipped a toe in the third dimension by standing the channel on edge like a shark’s fin, so the gate contacted it on three sides. The design reduced current leaking through in the off state and matched the performance of a traditional 2D transistor with a shorter channel—an equivalence to which the node size now hints. Patterning with extreme ultraviolet (EUV) light, which has a wavelength of 13.5 nanometers—almost as short as x-rays—enabled engineers to reach a density of 20 billion transistors per square centimeter.
Then, 5 years ago, IBM researchers replaced the finlike channel with three “nanosheets” of silicon 15 atomic layers thick stacked within the gate. That “gate all around” design increases the channel current and transistor performance of the so-called 2-nanometer chips that entered production last year at Samsung and Taiwan Semiconductor Manufacturing Company Limited, the world’s leading makers of microchips.
Now, IBM has gone further by essentially piling two layers of such nanosheet transistors in a “nanostack.” Engineers cannot simply deposit more materials on the first layer of transistors without ruining them. Instead, they bond a second wafer to the first one, and then etch the second in a complicated process that requires swapping the evolving chip from one supporting substrate to another. The entire strategy is made possible by the ability to bond the two wafers with a thin, exquisitely uniform insulating layer, Bu says.
IBM researchers stagger the two layers of transistors by a precise amount, which makes them easier to connect and helps reduce power consumption by 70%. “They’re doing wafers that are millimeters in size, but they can’t be off more than a nanometer or two,” Rondinelli says. “This is highly impressive.”
The technology can be pushed further, Bu predicts. “We can stack multiple layers,” he says, “but there are a few building blocks we need to develop and we’re working on those today.” For example, he says, to add more layers, engineers will have to design channels to ferry heat out of the chip.
To keep scaling up the transistor density, chip designers will also have to revisit basic materials issues, Nam says. For example, features will have to be smooth on the level of planes of atoms, he says, and that will be hard to achieve with current photoresists, which are polymers made of large molecules. Finding better resists is a hot area of research, Nam says.
Ultimately cost may be the factor that limits how many transistors can be packed onto a chip. According to a trend known as Moore’s second law, every time the number of transistors on a microchip doubles, so does the cost of the setup, or fab, required to make them. A fab for the current 2-nanometer technology reportedly costs $28 billion. But for the moment the AI boom is driving the microchip market, Nam says. “AI demand is so big there’s enough demand to justify these very expensive approaches.”