In December 1953, Electronics described the CRT computer memory array developed by US National Bureau of Standards. Even if Williams and Kilburn explained the operation of their system, basing upon the well-known theory of secondary-emitting surfaces, there were some not well-explained phenomena. Nevertheless, CRT memories, based upon the Williams storage system, were widely used for their high speed. In US, to take full advantage of their speed, memory banks were often built with a word-wide parallelism. In this case, a battery of 45 cathode ray tubes was used to store words wide 45 bit each. Read or write speeds of 21,000 words per second were obtained. By the way, similar speeds were also obtainable with some delay line memory units.
Several cathode ray tubes were satisfactory tried in the described array, 5UP1, 5UP11 and also 3KP1. Here are some pictures of the memory, showing a group of CRTs and details of a pair of tubes with shields removed; in these pictures also video amplifiers are visible below CRTs. The third picture shows the pattern of stored bits on a repeater monitor.
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A dot-dash mode of operation was chosen, dashes being written for the ‘one’ locations. The X and Y deflection plates of the 45 CR tubes were connected in parallel, driven by a staticizer/counter with two power DACs. 4 bits were used for the X-axis and 5 bits for Y, resulting in a total capacity of 512 words. Each DAC used three 807s in the output stage, to drive an equivalent load of 1200pF through a 100V swing, with 3µs settling time. A sequencer generated a 0.5µs write/read pulse to drive the grids of the CRTs, plus a 0.25µs read strobe pulse and a ramp superimposed on the Y deflection signal. If a ‘one’ was detected on the read strobe, the write pulse was stretched to 2.5µs. A block diagram of the memory system is given below, together with simplified schematics of the gating amplifier, which has a gain as high as 30,000, and of the X deflection circuit.
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In this system stored data need to be continuously regenerated: this function involves sequentially all the memory positions and is intermixed with the computer access. Every location access takes 12µs, regardless of whether it is a read/write or a refresh cycle. Therefore a new refresh of the entire array takes place every 6144 microseconds.
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