Quilter, a company focused on physics-driven AI for electronics design, has announced Project Speedrun, an initiative that demonstrated how AI-driven design tools can dramatically shorten traditional PCB development timelines. In the demo, a single engineer used Quilter’s physics-based AI platform to take a dual-board Linux computer from schematic to fabrication-ready layout in less than one week.
Quilter says Project Speedrun is the first computer designed by AI.
The design, centered on an NXP i.MX 8M Mini processor, includes 843 components across two boards. On the first attempt, it powered on and booted Debian successfully. Tasks that normally span several months of placement, routing, and iteration were completed with minimal manual intervention.
Physics-Driven AI: A Paradigm Shift for PCB Design
At the core of Project Speedrun is Quilter’s physics-driven AI engine, which treats PCB layout as a constrained optimization problem rather than a rule-based automation task. Instead of relying on predefined placement heuristics or post-route cleanup, the system evaluates signal integrity, power integrity, thermal behavior, and electromagnetic coupling concurrently during component placement and routing.
Each viable candidate is determined by the AI engine and displayed in a GUI format.
This allows electrical constraints to influence physical decisions from the earliest stages of layout rather than being validated only after routing is complete. The reference design centers on the NXP i.MX 8M Mini, a processor that has a mix of high-speed DDR interfaces, dense power distribution requirements, and mixed-signal peripherals. The final implementation spans two PCBs and integrates 843 components, including memory, interfaces, and supporting passives.
Quilter’s platform automatically handled component grouping, escape routing, impedance-controlled traces, and power plane topology while maintaining manufacturability constraints suitable for standard fabrication flows.
Automation Speeds the Process
A notable aspect of the demonstration is the limited need for manual intervention. After initial schematic import and constraint definition, the AI-generated layouts required only minor human review and adjustment before tape-out. Within Project Speedrun, the candidate tool systematically organizes large numbers of possible design configurations into a manageable set of viable options. These “candidates” represent specific combinations of topology, routing, and constraint choices that have a realistic chance of meeting performance requirements.
In the demo, the boards powered on and booted Linux on the first attempt. From a workflow perspective, Project Speedrun demonstrates that integrating physics-awareness directly into layout generation can reduce iteration cycles and improve first-pass success rates for complex embedded systems.
Can AI-Based PCB Design Work for High-Speed Designs?
While Project Speedrun demonstrates the potential of AI-assisted PCB layout to compress development timelines, it also highlights areas where human expertise remains critical. Integrating a tool like Quilter into existing design flows requires discipline, particularly for teams accustomed to manual control over placement and routing decisions.
An engineer using Quilter completed the two-board system with 38.5 hours of human input, replacing 428 hours of estimated manual effort.
These challenges become more pronounced as designs push into higher-speed regimes, where tighter timing margins and advanced power integrity requirements demand rigorous review and domain-specific judgment. High-speed design is difficult because performance margins collapse as data rates climb, leaving little room for error across the signal path. Loss, crosstalk, impedance discontinuities, and power integrity issues that were once secondary concerns quickly become first-order design constraints.
At these speeds, small layout decisions can have outsized effects on eye opening, jitter, and overall system reliability. As AI-driven layout tools like Project Speedrun mature, their long-term value will depend not only on speed gains but on how effectively they scale to next-generation interfaces while remaining compatible with established validation practices.
All images used courtesy of Quilter AI.