A 65-page in-depth research report on the next phase of device scaling.
Multi-die assemblies are the next phase of Moore’s Law, scaling up and out to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits.
But this is much harder than it sounds. Chiplets don’t just snap together like LEGOs, and so far nearly all of the multi-chiplet designs have been built from proprietary parts. What kinds of problems are leading-edge chipmakers encountering, how are they solving them, and what’s the future for a chiplet marketplace? Click on the first image below to read the chiplets eBook.
[Editor’s Note: Please sign up for our newsletters in the box to the right. We use only aggregate numbers — we never reveal any other information — to attract advertisers so we can continue delivering free high-quality content to you.]
Technical Advisory Board
• Rob Kruger, product management director, Synopsys
• Andy Heinig, group leader, advanced system integration, department head of
efficient electronics, Fraunhofer IIS/EAS
• Moshiko Emmer, distinguished engineer, silicon solutions group, Cadence
• Pratyush Kamal, director, central engineering solutions, Siemens
• Pax Wang, director for advanced packages, UMC
Related
Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
Chiplet Knowledge Center
On-Die And In-Package Interconnects: eBook
Chiplets Vs. Soft IP: Different In Almost Every Way
Bryon Moyer
(all posts)
Bryon Moyer is a technology editor at Semiconductor Engineering.