OPEN INITIATIVE · FAB DIGITAL TWIN · REALISTIC CAD
Architectural cleanroom layout, 121 OEM equipment engineering taxonomy across 13 process categories, cascading yield simulation, and SEMI E10 telemetry.
300mm
12-Inch Wafer Standard
8 Stages
Yield Model Stages
SECS/GEM
Industrial Telemetry
Open Data & Research Infrastructure
Transparent OEM machine specifications, reproducible 300mm fab scheduling benchmarks, and an open equipment schema.
Open Equipment Catalog
Machine-readable specifications for 121 production tools from global OEM vendors across 13 process categories. Built on the 7-layer open schema.
Catalog Maturity & Contribution Funnel 121 Tools · 13 Categories
L1 Verified (Footprint & Manual) 6% · 7 tools
Draft (Awaiting Dimensions & Hookups) 94% · 114 tools
MIMAC-2026 Benchmark Testbed
An open, synthetic benchmark for 300mm fab scheduling research — 18 tool groups, 217 machines, three tasks (lot dispatching, AMHS routing, PM scheduling).
Tasks: Lot Dispatching · AMHS Routing · PM
Baselines: FIFO · SPT · EDD · CR
COMMUNITY CONTRIBUTION FUNNEL
Submit Equipment Specifications
Contribute missing facilities footprints, power/exhaust hookups, or drop-in replacement tool references. Enable instant 1-click 3D cleanroom evaluation.
Drop-in Replacement Mapping Map equipment against incumbent tools to prepare layout & performance comparison data
Open Submission & Verification Workflow Validate incoming specs against schema.json and 5 provenance tiers before publication
10-STEP FABRICATION CAD ARCHIVE
Interactive nanoscale fabrication digital twins for next-generation transistors and 3D memory cells.
5 Digital Twins
14nm / 7nm RMG
FinFET 3D Transistor
SADP fin etch, STI recess, SiGe epi, HKMG ALD gate replacement.
Explore 3D →
3nm / 2nm GAA
GAAFET Nanosheet 3D
Si/SiGe superlattice, inner spacer formation, nanosheet release, 360° gate.
Explore 3D →
6F² · >40:1 MIM
DRAM 1T1C Memory
Buried wordlines, bitline contacts, >40:1 HAR ZAZ MIM capacitors.
Explore 3D →
128+ Tier · CTF
3D NAND Flash (CTF)
ONON superlattice, >60:1 channel hole etch, Macaroni core, wordline slit cut.
Explore 3D →
16-Hi · >1.2 TB/s
HBM3E / HBM4 Stacking
TSV copper pillars, microbumps, 30μm ultra-thinning, MR-MUF 16-Hi stacking.
Explore 3D →
Bridging physical cleanroom architecture with microscopic semiconductor physics in an open digital framework.
Cleanroom Physical Spatial Twin
Instant toggle between architectural 2D floor plans and high-precision 3D cleanroom digital twin with raised perforated flooring and amber lithography core.
CLEANROOM CLASS 1 / ISO 3 Explore 3D →
Verified OEM Equipment Taxonomy
Accurate physical dimensions (W×L×H) and elevation drawings for leading brands: ASML, Lam, AMAT, TEL, KLA, Screen, and DISCO.
121 OEM TOOLS · 13 CATEGORIES View Elevations →
8-Stage Cascading Yield Engine
Surrogate physics model linking material purity, equipment aging, and inter-step queue times into real-time Fab yield and monthly capacity.
CASCADING YIELD WATERFALL Inspect Yield Waterfall →
SECS/GEM Real-Time Telemetry & FDC
SEMI E10 equipment operational state machine (Running, Idle, Down, Maintenance) with live sensor sparklines and fault injection scenarios.
SEMI E10 · 6 SCENARIOS Run Fault Injection →
MES · APC / SPC · YIELD MANAGEMENT SYSTEM (YMS)
Integrating open-source industrial tools, SEMI communication protocols, and physics-based models into an open semiconductor digital ecosystem.
SEMI MES & AMHS Logistics
ISA-95 Level 3 execution with SEMI E40/E87/E90/E94 standards, FOUP carrier tracking, and automated fab dispatching.
SECS/GEM Protocol:secsgem (Python)
Fab Dispatching:Google OR-Tools
Discrete Event Sim:SimPy / salabim
Statistical Process Control (SPC/FDC)
Shewhart control charts, Nelson 8 run rules, real-time Cp/Cpk capability, and chamber sensor fault detection.
SPC & Capability:pyspc · mfgQC
In-DB SQL Control:spc-kit (PostgreSQL)
Chamber Anomaly:PyOD · tsfresh
Yield Management & Spatial Defects
WM-811K benchmark defect patterns, 300mm die bin maps, STDF V4 datalog parsing, and Poisson/Murphy yield models.
STDF V4 Datalog:PySTDF · rust-stdf
Wafer Map Render:wafermap (WebGL)
Defect Classifier:WM-811K CNN
Interactive 300mm Wafer Map & Spatial Defect Classifier LIVE DEMO
Test Edge-Ring, Center, Scratch, and Donut defect fingerprints, observe theoretical Poisson vs. Murphy yield calculations, and inspect STDF logs.
KNOWLEDGE BASE & ARCHITECTURE FAQ
Direct technical definitions, cleanroom standards, and architectural specifications of the SemiconFab.org platform.
01 What is SemiconFab.org?
SemiconFab.org is an open-access engineering digital twin platform for 300mm (12-inch) semiconductor wafer fabrication cleanrooms. It models architectural cleanroom elevations, subfab MEP (mechanical, electrical, plumbing) utility networks, a 121 OEM equipment engineering taxonomy across 13 process categories, real-time SECS/GEM & SEMI E10 industrial telemetry, and microscopic yield analytics directly in the browser.
02 What cleanroom and architectural standards are modeled?
The platform follows SEMI standards and ISO 14644-1 Class 1 cleanroom specifications (< 10 particles/m³ for particles ≥ 0.1 µm). It models a 4.5m process cleanroom with raised waffle-slab access flooring (600mm × 600mm perforated tiles), an amber-lit photolithography core, fan filter units (FFU), and a 6.0m subfab utility basement (Class 10,000 / ISO 7) for vacuum pumps, RF generators, and scrubbers.
03 Which semiconductor equipment categories and OEM tools are included?
The taxonomy covers 121 OEM equipment models across 13 semiconductor manufacturing categories: Photolithography (EUV 13.5nm, ArFi 193nm, KrF), Photoresist Track, Dry Etching (RIE, ICP, ALE), Thin Films (PECVD, LPCVD, ALD, PVD, ECD), Wet Cleaning, CMP, Thermal Processing, Ion Implantation, Metrology, Defect Inspection, Advanced Packaging, Test, and Other.
04 How does the Yield Management System (YMS) & Defect Simulator work?
The YMS simulator implements Poisson (Y = exp(-D0 · A)) and Murphy yield models across an 8-stage cascading wafer
flow. It includes interactive WebGL 300mm wafer maps that render
WM-811K benchmark spatial defect fingerprints (Edge-Ring,
Center, Scratch, Donut, Random) and STDF V4 datalog parsing.
05 What industrial standards and telemetry protocols are supported?
The platform supports SEMI E10 equipment reliability states (Productive, Standby, Scheduled Down, Unscheduled Down), SECS/GEM (SEMI E30/E37 HSMS) equipment communication variables (SVID/CEID), and standard semiconductor factory automation interfaces.
06 Is SemiconFab.org free and open to universities and research institutions?
Yes. SemiconFab.org is committed to open access for semiconductor engineering education, cleanroom workforce training, and digital twin research. It runs entirely inside standard web browsers without downloads or proprietary CAD software required.