CN119301758A - A metal integration method for manufacturing integrated devices - Google Patents
A metal integration method for manufacturing integrated devices Download PDFInfo
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- CN119301758A CN119301758A CN202280096666.4A CN202280096666A CN119301758A CN 119301758 A CN119301758 A CN 119301758A CN 202280096666 A CN202280096666 A CN 202280096666A CN 119301758 A CN119301758 A CN 119301758A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a permanent auxiliary member being left in the finished device, e.g. aids for protecting the bonding area during or after the bonding process
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Abstract
Fabrication of integrated devices (e.g., integrated semiconductor devices) is disclosed herein. The metal integration method may be used in a process flow for manufacturing such an integrated device. The method is based on patterning different spacers and using the spacers to define different metal structures in two separate steps. Specifically, the processing steps of the metal structure of the first metal material (61) and the metal structure of the second metal material (91) are different.
Description
技术领域Technical Field
本公开涉及集成器件，例如集成半导体器件的制造。本公开提供了一种金属集成方法，该方法可用于制造这种集成器件的工艺流程中。The present disclosure relates to the manufacture of integrated devices, such as integrated semiconductor devices, and provides a metal integration method that can be used in a process flow for manufacturing such integrated devices.
背景技术Background Art
在用于制造集成器件的工艺流程中，高级后道工艺(back end of line，BEOL)图案化可以使用小于21nm的金属间距。对于这种高级图案化，边缘放置误差(edge placementerror，EPE)是关键，并且需要完全自对准过孔，以确保不同金属层之间的鲁棒连接。然而，可以观察到，当使用深紫外(deep ultraviolet，DUV)图案化技术时，没有足够的EPE裕度用于这种高级图案化。这是因为由于固有的技术限制，不可能将EPE裕度缩小到5nm以下。In the process flow for manufacturing integrated devices, advanced back end of line (BEOL) patterning can use metal pitches less than 21nm. For this advanced patterning, edge placement error (EPE) is key, and fully self-aligned vias are required to ensure robust connections between different metal layers. However, it can be observed that when using deep ultraviolet (DUV) patterning technology, there is not enough EPE margin for this advanced patterning. This is because it is impossible to reduce the EPE margin below 5nm due to inherent technological limitations.
除了金属线的缩放之外，BEOL功能中的主要瓶颈之一是过孔图案化及其对准。主要铸造厂已经实现了多个自对准过孔和完全自对准过孔(fully self-aligned-via，FSAV)示例方案，以减轻EPE的限制。所有实现的方案都使用单一硬掩模材料。这些方案可以在5nm节点(金属间距为28nm)下获得良好的结果，但前提是实现了极紫外(extremeultraviolet，EUV)技术。这是因为采用单一硬掩膜材料来保护相邻的金属线并放宽对EPE的要求。然而，由于在5nm以下很难实现EPE，因此对于小于21nm的金属间距，目前还没有方案。In addition to the scaling of metal lines, one of the main bottlenecks in BEOL functions is via patterning and its alignment. Major foundries have implemented multiple self-aligned vias and fully self-aligned-via (FSAV) example schemes to alleviate the limitations of EPE. All implemented schemes use a single hard mask material. These schemes can achieve good results at the 5nm node (metal pitch of 28nm), but only if extreme ultraviolet (EUV) technology is implemented. This is because a single hard mask material is used to protect adjacent metal lines and relax the requirements for EPE. However, since EPE is difficult to achieve below 5nm, there is currently no solution for metal pitches less than 21nm.
发明内容Summary of the invention
鉴于以上所述，本公开旨在提供一种改进的金属集成方案，所述方案可用于制造集成器件的工艺流程中。目的是为各种金属间距提供方案，例如，也为21nm以下的金属间距提供方案。另一个目的是解决低于5nm的EPE裕度的情况。In view of the above, the present disclosure aims to provide an improved metal integration scheme that can be used in the process flow of manufacturing integrated devices. The purpose is to provide solutions for various metal spacings, for example, also for metal spacings below 21nm. Another purpose is to solve the situation of EPE margin below 5nm.
这些和其它目的通过独立权利要求中描述的本公开方案来实现。有利的实现方式在从属权利要求中进一步定义。These and other objects are achieved by the disclosed solutions described in the independent claims. Advantageous implementations are further defined in the dependent claims.
本公开提出了一种用于金属集成的双材料硬掩模工艺，所述工艺使得能够在BEOL金属化工艺期间对相邻的金属线进行保护。The present disclosure proposes a dual material hard mask process for metal integration that enables protection of adjacent metal lines during BEOL metallization processes.
本公开的第一方面提供了一种用于制造集成器件的金属集成方法，所述方法包括：在衬底上由公共层形成第一结构和第二结构，其中所述第一结构和所述第二结构沿第一方向彼此分离并各自延伸至第二方向；在所述衬底上形成第一间隔件和第二间隔件，其中所述第一间隔件和所述第二间隔件各自延伸至所述第二方向，所述第一间隔件在所述第一结构的两侧衬砌所述第一结构，所述第二间隔件在所述第二结构的两侧衬砌所述第二结构；在所述衬底上形成第三间隔件和第四间隔件，其中所述第三间隔件和所述第四间隔件各自延伸至所述第二方向，所述第三间隔件在所述第一间隔件的两侧衬砌所述第一间隔件，所述第四间隔件在所述第二间隔件的两侧衬砌所述第二间隔件；在所述第三间隔件和所述第四间隔件之间形成第五间隔件；通过选择性地移除所述第三间隔件、所述第四间隔件、所述第一结构和所述第二结构来形成多个第一间隙；将第一金属材料沉积到所述第一间隙中；通过选择性地移除所述第一间隔件和所述第二间隔件来形成多个第二间隙；将第一介电材料沉积到所述第二间隙中；在所述第二间隙中的所述第一介电材料中形成多个沟槽；将第二金属材料沉积到所述沟槽中。A first aspect of the present disclosure provides a metal integration method for manufacturing an integrated device, the method comprising: forming a first structure and a second structure from a common layer on a substrate, wherein the first structure and the second structure are separated from each other along a first direction and each extends to a second direction; forming a first spacer and a second spacer on the substrate, wherein the first spacer and the second spacer each extend to the second direction, the first spacer lines the first structure on both sides of the first structure, and the second spacer lines the second structure on both sides of the second structure; forming a third spacer and a fourth spacer on the substrate, wherein the third spacer and the fourth spacer each extend to the second direction , the third spacer lines the first spacer on both sides of the first spacer, and the fourth spacer lines the second spacer on both sides of the second spacer; a fifth spacer is formed between the third spacer and the fourth spacer; a plurality of first gaps are formed by selectively removing the third spacer, the fourth spacer, the first structure and the second structure; a first metal material is deposited into the first gap; a plurality of second gaps are formed by selectively removing the first spacer and the second spacer; a first dielectric material is deposited into the second gap; a plurality of grooves are formed in the first dielectric material in the second gap; a second metal material is deposited into the grooves.
所述第一结构和所述第二结构可以以给定的间距重复。所述第一结构和所述第二结构可以是所述集成器件的单位晶胞的部分，其中所述单位晶胞可以重复一次或多次。所述第一结构可以是第一导电结构，例如第一金属结构。所述第二结构可以是第二导电结构，例如第二金属结构。相应地，所述第一结构和所述第二结构可以由相同的导电层制成，例如金属层。所述第一结构和所述第二结构也可以是基于氮化物的结构，例如氮化硅结构，也可以是基于碳的结构，例如无定形碳(amorphous carbon，a-C)结构。The first structure and the second structure may be repeated at a given pitch. The first structure and the second structure may be parts of a unit cell of the integrated device, wherein the unit cell may be repeated once or multiple times. The first structure may be a first conductive structure, such as a first metal structure. The second structure may be a second conductive structure, such as a second metal structure. Accordingly, the first structure and the second structure may be made of the same conductive layer, such as a metal layer. The first structure and the second structure may also be nitride-based structures, such as silicon nitride structures, or carbon-based structures, such as amorphous carbon (a-C) structures.
通过形成各种空间，并通过使用这些间隔件分别处理所述第一金属材料和所述第二金属材料的结构，就能为各种金属间距提供方案，也能为21nm以下的金属间距提供方案。可以使用DUV技术，也可以使用EUV技术，但不是必需的。By forming various spaces and using these spacers to process the structures of the first metal material and the second metal material respectively, solutions can be provided for various metal pitches, and also for metal pitches below 21nm. DUV technology can be used, and EUV technology can also be used, but it is not necessary.
在所述第一方面的一种实现方式中，所述方法还包括：在选择性地移除所述第三间隔件、所述第四间隔件、所述第一结构和所述第二结构之后：将第一填充材料沉积到所述第一间隙中；移除所述第一填充材料以重新打开所述第一间隙；其中所述第一金属材料沉积到所述重新打开的第一间隙中。In an implementation of the first aspect, the method further includes: after selectively removing the third spacer, the fourth spacer, the first structure and the second structure: depositing a first filling material into the first gap; removing the first filling material to reopen the first gap; wherein the first metal material is deposited into the reopened first gap.
在所述第一方面的一种实现方式中，所述方法还包括：在选择性地移除所述第一间隔件和所述第二间隔件之前：选择性地在所述第三间隔件或所述第四间隔件或所述第一填充材料中分别形成一个或多个开口；将所述开口延伸到所述衬底中；其中将所述第一金属材料沉积到所述第一间隙中包括将所述第一金属材料沉积到延伸到所述衬底中的所述开口中，以形成一个或多个第一过孔。In an implementation of the first aspect, the method also includes: before selectively removing the first spacer and the second spacer: selectively forming one or more openings in the third spacer or the fourth spacer or the first filling material, respectively; extending the openings into the substrate; wherein depositing the first metal material into the first gap includes depositing the first metal material into the opening extending into the substrate to form one or more first vias.
相应地，可以以自对准的方式处理第一过孔。Accordingly, the first via hole can be processed in a self-aligned manner.
在所述第一方面的一种实现方式中，所述方法还包括，在将所述第二金属材料沉积到所述沟槽中之前：将一个或多个所述沟槽延伸穿过所述第一介电材料并进入所述衬底中；其中将所述第二金属材料沉积到所述沟槽中包括将所述第二金属材料沉积到延伸到所述衬底中的所述沟槽中，以形成一个或多个第二过孔。In an implementation of the first aspect, the method further includes, before depositing the second metal material into the groove: extending one or more of the grooves through the first dielectric material and into the substrate; wherein depositing the second metal material into the groove includes depositing the second metal material into the groove extending into the substrate to form one or more second vias.
相应地，可以以自对准的方式处理第二过孔。Accordingly, the second via hole can be processed in a self-aligned manner.
在所述第一方面的一种实现方式中，通过以下方式在所述第三间隔件中、或在所述第四间隔件中、或在所述第一填充材料中形成所述一个或多个开口：光刻图案化；对所述第三间隔件或所述第四间隔件或所述第一填充材料执行第一选择性蚀刻，以形成所述一个或多个开口；对所述衬底执行第二选择性蚀刻，以将所述一个或多个开口延伸到所述衬底中。In an implementation of the first aspect, the one or more openings are formed in the third spacer, or in the fourth spacer, or in the first filling material by: photolithography patterning; performing a first selective etching on the third spacer, the fourth spacer, or the first filling material to form the one or more openings; performing a second selective etching on the substrate to extend the one or more openings into the substrate.
在所述第一方面的一种实现方式中，所述方法还包括：在选择性地移除所述第三间隔件或所述第四间隔件之前，或在移除所述第一填充材料之前：用保护层覆盖所述第三间隔件或所述第四间隔件或所述第一填充材料的部分，以防止所述第三间隔件或所述第四间隔件或所述第一填充材料的该部分被移除。In an implementation of the first aspect, the method further includes: before selectively removing the third spacer or the fourth spacer, or before removing the first filling material: covering a portion of the third spacer or the fourth spacer or the first filling material with a protective layer to prevent the portion of the third spacer or the fourth spacer or the first filling material from being removed.
在所述第一方面的一种实现方式中，所述方法还包括：在选择性地移除所述第一间隔件和所述第二间隔件之前：将所述第一金属材料凹陷到所述第一间隙中；将第一硬掩模材料沉积到所述第一间隙中覆盖所述凹陷的第一金属材料。In an implementation of the first aspect, the method further includes: before selectively removing the first spacer and the second spacer: recessing the first metal material into the first gap; and depositing a first hard mask material into the first gap to cover the recessed first metal material.
在所述第一方面的一种实现方式中，所述一个或多个沟槽通过以下方式延伸到所述衬底中：将第二填充材料沉积到所述多个沟槽中；光刻图案化；对所述一个或多个沟槽中的所述第二填充材料执行第一选择性蚀刻；对所述介电材料执行第二选择性蚀刻，以将所述一个或多个沟槽延伸穿过所述介电材料并进入所述衬底中；移除所述第二填充材料。In an implementation of the first aspect, the one or more grooves extend into the substrate by: depositing a second filling material into the plurality of grooves; photolithography patterning; performing a first selective etching on the second filling material in the one or more grooves; performing a second selective etching on the dielectric material to extend the one or more grooves through the dielectric material and into the substrate; and removing the second filling material.
在所述第一方面的一种实现方式中，所述方法还包括：在将所述第二金属材料沉积到所述沟槽中之后：选择性地移除所述第二金属材料的部分；将第二介电材料沉积到选择性地移除了所述第二金属材料的位置。In an implementation of the first aspect, the method further includes: after depositing the second metal material into the groove: selectively removing a portion of the second metal material; and depositing a second dielectric material to the position where the second metal material was selectively removed.
在所述第一方面的一种实现方式中，所述选择性地移除所述第二金属材料的所述部分包括：光刻图案化以仅暴露所述第二金属材料的所述部分；对所述暴露的第二金属材料执行选择性金属蚀刻。In an implementation of the first aspect, the selectively removing the portion of the second metal material includes: photolithography patterning to expose only the portion of the second metal material; and performing selective metal etching on the exposed second metal material.
在所述第一方面的一种实现方式中，所述方法包括：在将所述第二金属材料沉积到所述沟槽中之前：在所述沟槽的部分中形成第三介电材料，以防止所述第二金属材料沉积到所述沟槽的该部分中。In an implementation of the first aspect, the method includes: before depositing the second metal material into the trench: forming a third dielectric material in a portion of the trench to prevent the second metal material from being deposited into the portion of the trench.
在所述第一方面的一种实现方式中，所述方法还包括：凹陷所述暴露的第二金属材料；将第二硬掩模材料沉积到所述凹陷的第二金属材料中。In an implementation manner of the first aspect, the method further includes: recessing the exposed second metal material; and depositing a second hard mask material into the recessed second metal material.
在所述第一方面的一种实现方式中，所述第一间隔件和所述第二间隔件的材料与所述第三间隔件和所述第四间隔件的材料是不同的材料；和/或所述第一金属材料和所述第二金属材料是不同的材料。In an implementation of the first aspect, the material of the first spacer and the second spacer is different from the material of the third spacer and the fourth spacer; and/or the first metal material and the second metal material are different materials.
在所述第一方面的一种实现方式中，所述第一金属材料和/或所述第二金属材料包括以下至少一种：钌、铜、钼、钴和钨。In an implementation manner of the first aspect, the first metal material and/or the second metal material includes at least one of the following: ruthenium, copper, molybdenum, cobalt and tungsten.
在所述第一方面的一种实现方式中，所述方法还包括：所述衬底包括以下至少一个：中道工艺(middle of line，MOL)层和BEOL层。In an implementation manner of the first aspect, the method further includes: the substrate includes at least one of the following: a middle of line (MOL) layer and a BEOL layer.
在所述第一方面的一种实现方式中，所述第一介电材料包括氮化硅和/或用于所述MOL层的电介质。In an implementation of the first aspect, the first dielectric material includes silicon nitride and/or a dielectric for the MOL layer.
在所述第一方面的一种实现方式中，所述衬底包括一个或多个集成电路；所述第一结构和/或所述第二结构是所述衬底中的至少一个集成电路的电源轨。In an implementation of the first aspect, the substrate includes one or more integrated circuits; the first structure and/or the second structure is a power rail of at least one integrated circuit in the substrate.
本公开的第二方面提供了一种集成器件，所述集成器件可由根据所述第一方面或所述第一方面的任何一种实现方式的方法获取。A second aspect of the present disclosure provides an integrated device, which can be obtained by a method according to the first aspect or any implementation manner of the first aspect.
根据第二方面所述的集成器件可以具有低于21nm的金属间距。然而，其它金属间距，例如，低于32nm的金属间距也是可能的。The integrated device according to the second aspect may have a metal pitch below 21 nm. However, other metal pitches, for example, metal pitches below 32 nm are also possible.
根据上述内容，本公开的方案提出了一种新的金属集成方案，所述方案使得能够制造具有低于21nm的小金属间距的不同金属结构(例如，窄金属线)，即使在使用DUV技术而不是EUV技术时也是如此。具体地，这是通过实现新颖的间隔件界定图案化方案(使用第一到第五间隔件)来在两个分开的步骤中界定金属结构来实现的。第一金属材料可以蚀刻(或沟槽填充)，第二金属材料可以通过不同步骤中的金属填充工艺来界定。在金属沉积之后，可以凹陷金属，或者可以实现区域选择性沉积(area selective deposition，ASD)来界定用于FSAV工艺的硬掩模的两种分离材料。Based on the above, the scheme of the present disclosure proposes a new metal integration scheme that enables the manufacture of different metal structures (e.g., narrow metal lines) with small metal pitches below 21nm, even when using DUV technology instead of EUV technology. Specifically, this is achieved by implementing a novel spacer-defined patterning scheme (using first to fifth spacers) to define the metal structure in two separate steps. The first metal material can be etched (or trench filled) and the second metal material can be defined by a metal filling process in a different step. After metal deposition, the metal can be recessed, or area selective deposition (ASD) can be implemented to define the two separate materials of the hard mask for the FSAV process.
本公开的方案至少具有如下优点：The solution disclosed in the present invention has at least the following advantages:
·窄金属结构可以使用DUV进行集成，这可以通过在两个分离的工艺序列中分离第一金属材料和第二金属材料的集成来实现。Narrow metal structures can be integrated using DUV, which can be achieved by separating the integration of the first metal material and the second metal material in two separate process sequences.
·对于高级BEOL金属化(例如，对于21nm以下的金属间距)，可以提高EPE裕度，这可以通过在相邻的金属结构顶部使用不同材料的硬掩模来实现，这样就可能通过硬掩膜材料的高蚀刻选择性来实现真正的FSAV。For advanced BEOL metallization (e.g., for metal pitches below 21nm), the EPE margin can be improved. This can be achieved by using a hard mask of a different material on top of the adjacent metal structures, which makes it possible to achieve true FSAV through the high etch selectivity of the hard mask material.
·可以减小金属结构的电容，因为相邻的金属结构可能不在同一水平面上，但可以略微交错或在侧面有边缘重叠。The capacitance of metal structures can be reduced because adjacent metal structures may not be on the same level but can be slightly staggered or have edges overlapping on the sides.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
结合所附附图，下面实施例的描述将阐述上述各个方面及其实现方式，在附图中：In conjunction with the accompanying drawings, the following description of the embodiments will illustrate the above aspects and their implementation methods. In the drawings:
图1至图9示出了根据本公开的用于制造集成器件的方法；1 to 9 illustrate a method for manufacturing an integrated device according to the present disclosure;
图10至图29示出了根据本公开的用于制造集成器件的第一示例性方法；10 to 29 illustrate a first exemplary method for manufacturing an integrated device according to the present disclosure;
图30至图49示出了根据本公开的用于制造集成器件的第二示例性方法。30 to 49 illustrate a second exemplary method for fabricating an integrated device according to the present disclosure.
具体实施方式DETAILED DESCRIPTION
图1至图9示出了根据本公开的用于制造集成器件的方法。具体地，示出了该方法的连续处理步骤。每个图分别示出了在本图中执行的处理步骤之后的集成器件的中间状态。所有图均示出了集成器件的截面图，其中集成器件沿x轴(x方向)和z轴(z方向)示出，如图左下角的坐标系所示。其中一些图还示出了集成器件的俯视图，其中集成器件沿坐标系的x轴(x方向)和y轴(y方向)示出，如图的左上角所示。Figures 1 to 9 show a method for manufacturing an integrated device according to the present disclosure. Specifically, the continuous processing steps of the method are shown. Each figure shows the intermediate state of the integrated device after the processing steps performed in the figure. All figures show a cross-sectional view of the integrated device, wherein the integrated device is shown along the x-axis (x-direction) and the z-axis (z-direction), as shown in the coordinate system in the lower left corner of the figure. Some of the figures also show a top view of the integrated device, wherein the integrated device is shown along the x-axis (x-direction) and the y-axis (y-direction) of the coordinate system, as shown in the upper left corner of the figure.
图1示出了在该方法的第一步骤中，由衬底13上的公共层形成第一结构11和第二结构11。第一结构11和第二结构12可以由金属或氮化硅或无定形碳制成，且沿第一方向(左下角所示的坐标系中的x方向)彼此分离，并各自延伸至第二方向(y方向)。第一结构11和第二结构12可以界定集成器件的核心。衬底13可以包括层间电介质，该层间电介质设置在半导体衬底上，例如硅基衬底或非晶硅衬底上。FIG1 shows that in the first step of the method, a first structure 11 and a second structure 12 are formed by a common layer on a substrate 13. The first structure 11 and the second structure 12 may be made of metal or silicon nitride or amorphous carbon, and are separated from each other along a first direction (the x direction in the coordinate system shown in the lower left corner), and each extends to a second direction (y direction). The first structure 11 and the second structure 12 may define the core of the integrated device. The substrate 13 may include an interlayer dielectric disposed on a semiconductor substrate, such as a silicon-based substrate or an amorphous silicon substrate.
该方法的最小特征尺寸可以定义为F。如图1所示，第一结构11和第二结构12可以分别具有3F的宽度(沿第一方向)。第一结构11和第二结构12之间的间距可以是14F，这些金属结构之间的间距是11F。值得注意的是，可以以这种方式制造两个以上的金属结构11、12，例如，以所述间距设置的多个金属结构11、12。该方法可以示出该多个金属结构11、12中的任何两个金属结构11、12。值得注意的是，第一结构11和第二结构12可以通过抗蚀剂沉积，然后光刻(曝光)，然后抗蚀剂显影，然后图案转印到下面的衬底13来形成。The minimum feature size of the method can be defined as F. As shown in Figure 1, the first structure 11 and the second structure 12 can have a width of 3F respectively (along the first direction). The spacing between the first structure 11 and the second structure 12 can be 14F, and the spacing between these metal structures is 11F. It is worth noting that more than two metal structures 11, 12 can be manufactured in this way, for example, a plurality of metal structures 11, 12 arranged at the said spacing. The method can illustrate any two metal structures 11, 12 of the plurality of metal structures 11, 12. It is worth noting that the first structure 11 and the second structure 12 can be formed by resist deposition, followed by photolithography (exposure), followed by resist development, and then pattern transfer to the underlying substrate 13.
图2示出了在该方法的另一个步骤中，在衬底13上形成第一间隔件21和第二间隔件22。第一间隔件21和第二间隔件22均延伸至第二方向。第一间隔件21在第一结构11的两侧衬砌第一结构11，例如，第一间隔件21在第一方向上夹住第一结构11。第二间隔件22在第二结构12的两侧衬砌第二结构12，例如，第二间隔件22在第一方向上夹住第二结构12。第一间隔件21和第二间隔件22可以通过沉积间隔件材料并随后蚀刻该间隔件材料而形成。第一间隔件21和第二间隔件22可以分别在第一结构11和第二结构12的每一侧上具有沿第一方向的3F宽度。FIG2 shows that in another step of the method, a first spacer 21 and a second spacer 22 are formed on a substrate 13. The first spacer 21 and the second spacer 22 both extend to the second direction. The first spacer 21 lines the first structure 11 on both sides of the first structure 11, for example, the first spacer 21 clamps the first structure 11 in the first direction. The second spacer 22 lines the second structure 12 on both sides of the second structure 12, for example, the second spacer 22 clamps the second structure 12 in the first direction. The first spacer 21 and the second spacer 22 can be formed by depositing a spacer material and then etching the spacer material. The first spacer 21 and the second spacer 22 can have a width of 3F along the first direction on each side of the first structure 11 and the second structure 12, respectively.
图3示出了在该方法的另一个步骤中，在衬底13上形成第三间隔件31和第四间隔件32。第三间隔件31和第四间隔件32分别延伸至第二方向。第三间隔件31在第一间隔件21的两侧衬砌第一间隔件21，例如，第三间隔件31在第一方向上夹住第一间隔件21和第一结构11。第四间隔件32在第二间隔件22的两侧衬砌第二间隔件22，例如，第四间隔件32在第一方向上夹住第二间隔件22和第二结构12。第三间隔件31和第四间隔件32可以通过沉积第二间隔件材料并随后蚀刻该第二间隔件材料而形成。第三间隔件31和第四间隔件32可以分别在第一间隔件21和第二间隔件22的每一侧具有沿第一方向的1F宽度。FIG3 shows that in another step of the method, a third spacer 31 and a fourth spacer 32 are formed on the substrate 13. The third spacer 31 and the fourth spacer 32 extend to the second direction, respectively. The third spacer 31 lines the first spacer 21 on both sides of the first spacer 21, for example, the third spacer 31 clamps the first spacer 21 and the first structure 11 in the first direction. The fourth spacer 32 lines the second spacer 22 on both sides of the second spacer 22, for example, the fourth spacer 32 clamps the second spacer 22 and the second structure 12 in the first direction. The third spacer 31 and the fourth spacer 32 can be formed by depositing a second spacer material and then etching the second spacer material. The third spacer 31 and the fourth spacer 32 can have a width of 1F along the first direction on each side of the first spacer 21 and the second spacer 22, respectively.
图4示出了在该方法的另一个步骤中，在第三间隔件31和第四间隔件32之间形成第五间隔件41，从而也分别在第一间隔件21和第二间隔件22之间以及在第一结构11和第二结构12之间形成第五间隔件41。具体地，可以通过执行间隙填充来形成第五间隔件41，例如，其中衬底13上的所有间隙用与用于第一间隔件21和第二间隔件22相同的间隔件材料填充。然后，可以执行平坦化步骤(例如，化学机械抛光(chemical mechanical polishing，CMP))以平坦化中间集成器件的表面。4 shows that in another step of the method, a fifth spacer 41 is formed between the third spacer 31 and the fourth spacer 32, thereby also forming the fifth spacer 41 between the first spacer 21 and the second spacer 22 and between the first structure 11 and the second structure 12, respectively. Specifically, the fifth spacer 41 can be formed by performing gap filling, for example, in which all gaps on the substrate 13 are filled with the same spacer material as used for the first spacer 21 and the second spacer 22. Then, a planarization step (e.g., chemical mechanical polishing (CMP)) can be performed to planarize the surface of the intermediate integrated device.
图5示出了在该方法的另一个步骤中，通过选择性地移除第三间隔件31、第四间隔件32、第一结构11和第二结构12来形成多个第一间隙51。该步骤可以称为间隔和拉芯。图5示出了中间集成器件的俯视图和截面图，虚线表示截面图的切口位置。这在示出两个视图的所有其它图中都是相同的。FIG5 shows that in another step of the method, a plurality of first gaps 51 are formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11 and the second structure 12. This step can be called spacing and core pulling. FIG5 shows a top view and a cross-sectional view of the intermediate integrated device, and the dotted line indicates the cut position of the cross-sectional view. This is the same in all other figures showing two views.
图6示出了在该方法的另一个步骤中，将第一金属材料61沉积到第一间隙51中。第一金属材料61可以称为金属A，且该步骤可以包括金属A填充物和随后的CMP。6 shows that in another step of the method, a first metal material 61 is deposited into the first gap 51. The first metal material 61 may be referred to as metal A, and this step may include a metal A fill and subsequent CMP.
图7示出了在该方法的另一个步骤中，通过选择性地移除第一间隔件21和第二间隔件22来形成多个第二间隙71。该步骤可以称为间隔拉动步骤。第二间隙71形成于已沉积第一金属材料61的位置之间。7 shows that in another step of the method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22. This step may be referred to as a gap pulling step. The second gaps 71 are formed between locations where the first metal material 61 has been deposited.
图8示出了在该方法的另一个步骤中，在第二间隙71中沉积第一介电材料81，并且在第二间隙71中的第一介电材料81中形成多个沟槽82。沟槽82可以各自延伸到第二方向，并且可以形成在已沉积第一材料61的位置(沿第一方向)之间。8 shows that in another step of the method, a first dielectric material 81 is deposited in the second gap 71, and a plurality of trenches 82 are formed in the first dielectric material 81 in the second gap 71. The trenches 82 may each extend to the second direction, and may be formed between locations (along the first direction) where the first material 61 has been deposited.
图9示出了在该方法的另一个步骤中，将第二金属材料91沉积到沟槽82中。第二金属材料91可以称为金属B，且该步骤可以包括金属B填充物和随后的CMP。9 shows that in another step of the method, a second metal material 91 is deposited into the trench 82. The second metal material 91 may be referred to as metal B, and this step may include a metal B fill and subsequent CMP.
从说明该方法的图可以看出，图9所示的中间集成器件中的所有金属结构(分别由金属A和金属B形成)之间的间距比14F的初始间距小得多。例如，图9的步骤后的间距可以是3F。As can be seen from the diagram illustrating the method, the spacing between all metal structures (formed by metal A and metal B, respectively) in the intermediate integrated device shown in Figure 9 is much smaller than the initial spacing of 14F. For example, the spacing after the step of Figure 9 can be 3F.
图10至图29示出了根据本公开的用于制造集成器件的第一示例性方法，具体地，示出了在图1至图4中所示的方法的步骤之后发生的步骤。即，第一示例性方法包括图1至图4中所示的步骤和图10至图29中所示的步骤。此处省略对前者的重复描述。10 to 29 illustrate a first exemplary method for manufacturing an integrated device according to the present disclosure, and specifically, illustrate steps occurring after the steps of the method shown in FIGS. 1 to 4. That is, the first exemplary method includes the steps shown in FIGS. 1 to 4 and the steps shown in FIGS. 10 to 29. A repeated description of the former is omitted here.
图10示出了在第一示例性方法的另一个步骤中，执行光刻图案化。光刻图案化可以称为过孔图案化，因为该技术可用于图案化一个或多个第一过孔。具体地，中间集成器件用抗蚀剂101或类似物覆盖，然后选择性地显影和移除该抗蚀剂101或类似物以打开底层器件的特定区域102以用于进一步处理。例如，如图所示，第一间隔件21和第三间隔件31的部分暴露在外。也可以以类似的方式(未示出)暴露第二间隔件22和第四间隔件32的部分。FIG. 10 shows that in another step of the first exemplary method, photolithographic patterning is performed. Photolithographic patterning can be referred to as via patterning because the technique can be used to pattern one or more first vias. Specifically, the intermediate integrated device is covered with a resist 101 or the like, and then the resist 101 or the like is selectively developed and removed to open a specific area 102 of the underlying device for further processing. For example, as shown in the figure, portions of the first spacer 21 and the third spacer 31 are exposed. Portions of the second spacer 22 and the fourth spacer 32 can also be exposed in a similar manner (not shown).
图11示出了在第一示例性方法的另一个步骤中，在第三间隔件31(如图所示)和/或第四间隔件32(未示出)中形成一个或多个开口121。例如，可以对第三间隔件31和/或第四间隔件32执行第一选择性蚀刻以形成一个或多个开口121。一个或多个开口121可以各自暴露衬底13。一个或多个开口121可以称为过孔开口，因为其目的可以是形成一个或多个第一过孔，如下文所述。11 shows that in another step of the first exemplary method, one or more openings 121 are formed in the third spacer 31 (as shown) and/or the fourth spacer 32 (not shown). For example, a first selective etching may be performed on the third spacer 31 and/or the fourth spacer 32 to form the one or more openings 121. The one or more openings 121 may each expose the substrate 13. The one or more openings 121 may be referred to as via openings because their purpose may be to form one or more first vias, as described below.
图12示出了在第一示例性方法的另一个步骤中，开口121延伸到衬底13中。例如，可以对衬底13执行第二选择性蚀刻，以将一个或多个开口121延伸到衬底13中。其目的可以是在衬底13中形成一个或多个第一过孔。12 shows that in another step of the first exemplary method, the openings 121 extend into the substrate 13. For example, a second selective etch may be performed on the substrate 13 to extend one or more openings 121 into the substrate 13. The purpose may be to form one or more first vias in the substrate 13.
图13示出了在第一示例性方法的另一个步骤中，移除抗蚀剂101，然后用保护层131覆盖第三间隔件31和/或第四间隔件32(两者均示出)的部分，以分别防止在随后的下一个步骤中移除第三间隔件31和/或第四间隔件32的该部分。当前步骤可以称为块图案化。13 shows that in another step of the first exemplary method, the resist 101 is removed and then a portion of the third spacer 31 and/or the fourth spacer 32 (both shown) is covered with a protective layer 131 to prevent the portion of the third spacer 31 and/or the fourth spacer 32 from being removed in a subsequent next step, respectively. The current step may be referred to as block patterning.
图14示出了在第一示例性方法的另一个步骤中，通过选择性地移除第三间隔件31、第四间隔件32、第一结构11和第二结构12来形成多个第一间隙51。该步骤可以称为间隔和拉芯。值得注意的是，保护层131防止第三间隔件31和/或第二间隔件32的部分被移除。14 shows that in another step of the first exemplary method, a plurality of first gaps 51 are formed by selectively removing the third spacer 31, the fourth spacer 32, the first structure 11 and the second structure 12. This step may be referred to as spacing and core pulling. It is noteworthy that the protective layer 131 prevents portions of the third spacer 31 and/or the second spacer 32 from being removed.
图15示出了在第一示例性方法的另一个步骤中，将第一金属材料61沉积到第一间隙51中。如图所示，将第一金属材料61沉积到第一间隙51中包括将第一金属材料61沉积到延伸到衬底13中的开口121中。这可以形成一个或多个第一过孔。15 shows that in another step of the first exemplary method, a first metal material 61 is deposited into the first gap 51. As shown, depositing the first metal material 61 into the first gap 51 includes depositing the first metal material 61 into the opening 121 extending into the substrate 13. This may form one or more first vias.
图16示出了在第一示例性方法的另一个步骤中，可以凹陷(朝向衬底13的方向)第一金属材料61(其已经沉积到第一间隙51中)。因此，该步骤可以称为金属A凹陷。16 shows that in another step of the first exemplary method, the first metal material 61 (which has been deposited into the first gap 51) may be recessed (in the direction of the substrate 13). Therefore, this step may be referred to as metal A recessing.
图17示出了在第一示例性方法10的另一个步骤中，将第一硬掩模材料171沉积到凹陷的第一金属材料61上。该步骤可以称为硬掩模A形成或硬掩模A选择性区域沉积。值得注意的是，第一硬掩模材料171可以不形成在第三间隔件31或第四间隔件32的其余部分上，或者可以从第三间隔件31或第四间隔件32的其余部分移除。17 shows that in another step of the first exemplary method 10, a first hard mask material 171 is deposited onto the recessed first metal material 61. This step may be referred to as hard mask A formation or hard mask A selective area deposition. It is worth noting that the first hard mask material 171 may not be formed on the remaining portion of the third spacer 31 or the fourth spacer 32, or may be removed from the remaining portion of the third spacer 31 or the fourth spacer 32.
图18示出了在第一示例性方法的另一个步骤中，通过选择性地移除设置在第一金属材料61和硬掩模材料171之间的第一间隔件21和第二间隔件22来形成多个第二间隙71。该步骤可以称为间隔拉动步骤。第三间隔件31和第四间隔件32的其余部分也可以在该步骤中移除。可以通过对相应材料进行选择性蚀刻来执行选择性移除。18 shows that in another step of the first exemplary method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22 disposed between the first metal material 61 and the hard mask material 171. This step may be referred to as a spacer pulling step. The remaining portions of the third spacers 31 and the fourth spacers 32 may also be removed in this step. The selective removal may be performed by selectively etching the corresponding materials.
图19示出了在第一示例性方法的另一个步骤中，将第一介电材料81沉积到第二间隙71中。此外，例如，通过蚀刻第一介电材料81，在第一介电材料81(其已沉积到第二间隙71中)中形成多个沟槽82。19 shows that in another step of the first exemplary method, a first dielectric material 81 is deposited into the second gap 71. In addition, a plurality of trenches 82 are formed in the first dielectric material 81 (which has been deposited into the second gap 71), for example, by etching the first dielectric material 81.
图20示出了在第一示例性方法的另一个步骤中，将填充材料201沉积到多个沟槽82中。该步骤可以称为填充和过孔B图案化。图案化可以包括在一个或多个区域上提供掩模材料202，每个区域位于一个沟槽82(示出了一个)的上方。这可以用于图案化一个过孔或第二过孔，如下文所述。FIG20 shows that in another step of the first exemplary method, a fill material 201 is deposited into a plurality of trenches 82. This step may be referred to as fill and via B patterning. Patterning may include providing a mask material 202 on one or more regions, each region being located above one trench 82 (one is shown). This may be used to pattern one via or a second via, as described below.
图21示出了在第一示例性方法的另一个步骤中，执行光刻图案化。该光刻图案化可以包括在中间集成器件(其不是在设置掩模材料202的位置形成的)的表面上涂抹抗蚀剂101，以及移除掩模材料202以通过掩模开口暴露先前覆盖的区域，具体地，该掩模开口暴露一个或多个沟槽82。此外，可以在暴露的一个或多个沟槽82中对填充材料201执行第一选择性蚀刻，以从这些一个或多个沟槽82中移除填充材料201。21 shows that in another step of the first exemplary method, photolithography patterning is performed. The photolithography patterning may include applying a resist 101 on the surface of the intermediate integrated device (which is not formed at the location where the mask material 202 is set), and removing the mask material 202 to expose the previously covered area through the mask opening, specifically, the mask opening exposes one or more grooves 82. In addition, a first selective etching of the filling material 201 can be performed in the exposed one or more grooves 82 to remove the filling material 201 from these one or more grooves 82.
图22示出了在第一示例性方法的另一个步骤中，可以对暴露的和蚀刻的介电材料81执行第二选择性蚀刻，以将一个或多个沟槽82延伸穿过介电材料81并进入衬底13中。这可以称为过孔B蚀刻。22 shows that in another step of the first exemplary method, a second selective etch may be performed on the exposed and etched dielectric material 81 to extend one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as a via B etch.
图23示出了在第一示例性方法的另一个步骤中，移除抗蚀剂101并移除填充材料201。FIG. 23 shows that in another step of the first exemplary method, the resist 101 is removed and the filling material 201 is removed.
图24示出了在第一示例性方法的另一个步骤中，将第二金属材料91沉积到沟槽82中。之后，可以执行平坦化步骤。这可以称为金属B填充，然后是CMP。延伸到衬底13中的一个或多个沟槽82中的第二材料91可以形成一个或多个第二过孔。FIG. 24 shows that in another step of the first exemplary method, a second metal material 91 is deposited into the trench 82. Afterwards, a planarization step may be performed. This may be referred to as metal B filling followed by CMP. The second material 91 extending into one or more trenches 82 in the substrate 13 may form one or more second vias.
图25示出了在第一示例性方法的另一个步骤中，执行光刻图案化以仅暴露第二金属材料91的部分251。FIG. 25 shows that in another step of the first exemplary method, photolithography patterning is performed to expose only a portion 251 of the second metal material 91 .
图26示出了在第一示例性方法的另一个步骤中，选择性地移除暴露的第二金属材料91的部分251。这可以称为通过直接金属蚀刻(direct metal etch，DME)对金属B进行自对准切割。移除的第二金属材料91下方的介电材料81可以自由设置。26 shows that in another step of the first exemplary method, a portion 251 of the exposed second metal material 91 is selectively removed. This can be referred to as self-aligned cutting of metal B by direct metal etch (DME). The dielectric material 81 under the removed second metal material 91 can be freely disposed.
图27示出了在第一示例性方法的另一个步骤中，将第二介电材料271沉积到选择性地移除了第二金属材料91的位置。FIG. 27 shows that in another step of the first exemplary method, a second dielectric material 271 is deposited to the location where the second metal material 91 was selectively removed.
图28示出了在第一示例性方法的另一个步骤中，可以在衬底13的方向上凹陷暴露的第二金属材料91。这可以称为金属B凹陷。28 shows that in a further step of the first exemplary method, the exposed second metal material 91 may be recessed in the direction of the substrate 13. This may be referred to as metal B recessing.
图29示出了在第一示例性方法的另一个步骤中，将第二硬掩模材料291沉积到凹陷的第二金属材料91中。这可以称为硬掩模B形成或硬掩模B选择性区域沉积。29 shows that in another step of the first exemplary method, a second hard mask material 291 is deposited into the recessed second metal material 91. This may be referred to as hard mask B formation or hard mask B selective area deposition.
图30至图49示出了根据本公开的用于制造集成器件的第二示例性方法，具体地，示出了在图1至图4中所示的方法的步骤之后发生的步骤。即，第二示例性方法包括图1至图4中所示的步骤和图30至图49中所示的步骤。此处省略对前者的重复描述。30 to 49 illustrate a second exemplary method for manufacturing an integrated device according to the present disclosure, and specifically, illustrate steps occurring after the steps of the method shown in FIGS. 1 to 4. That is, the second exemplary method includes the steps shown in FIGS. 1 to 4 and the steps shown in FIGS. 30 to 49. A repeated description of the former is omitted here.
图30示出了在第二示例性方法的另一个步骤中，分别选择性地移除第三间隔件31和第四间隔件32以及第一结构11和第二结构12，其中在衬底13上方形成多个第一间隙51。30 shows that in another step of the second exemplary method, the third spacer 31 and the fourth spacer 32 and the first structure 11 and the second structure 12 are selectively removed, respectively, wherein a plurality of first gaps 51 are formed over the substrate 13 .
图31示出了在第二示例性方法的另一个步骤中，将填充材料311沉积到第一间隙51中，尤其是在第一间隔件21和第二间隔件22之间。随后可以执行CMP。31 shows that in another step of the second exemplary method, a filling material 311 is deposited into the first gap 51, in particular between the first spacer 21 and the second spacer 22. CMP may then be performed.
图32示出了在第二示例性方法的另一个步骤中，执行光刻图案化。光刻图案化可以称为过孔图案化，因为该技术可用于图案化一个或多个第一过孔。具体地，中间集成器件用抗蚀剂101或类似物覆盖，然后选择性地显影和移除该抗蚀剂101或类似物以打开底层器件的特定区域321以用于进一步处理。例如，如图所示，第一间隔件21和填充材料311的部分(第三间隔件31之前的位置)暴露在外。也可以以类似的方式暴露填充材料311的另一个部分(第四间隔件32之前的位置)。FIG32 shows that in another step of the second exemplary method, photolithographic patterning is performed. Photolithographic patterning can be referred to as via patterning because the technique can be used to pattern one or more first vias. Specifically, the intermediate integrated device is covered with a resist 101 or the like, and then the resist 101 or the like is selectively developed and removed to open a specific area 321 of the underlying device for further processing. For example, as shown in the figure, a portion of the first spacer 21 and the filling material 311 (the position before the third spacer 31) is exposed. Another portion of the filling material 311 (the position before the fourth spacer 32) can also be exposed in a similar manner.
图33示出了在第二示例性方法的另一个步骤中，在填充材料311中选择性地形成一个或多个开口121。例如，可以对填充材料311执行第一选择性蚀刻，以形成一个或多个开口121。这些开口可以称为过孔开口，因为这些开口的目的可能是制造第一过孔。33 shows that in another step of the second exemplary method, one or more openings 121 are selectively formed in the filling material 311. For example, a first selective etching may be performed on the filling material 311 to form the one or more openings 121. These openings may be referred to as via openings, because the purpose of these openings may be to manufacture first vias.
图34示出了在第二示例性方法的另一个步骤中，开口121延伸到衬底13中。例如，可以对衬底13执行第二选择性蚀刻，以将一个或多个开口121延伸到衬底13中。这可以称为第一过孔的过孔蚀刻。34 shows that in another step of the second exemplary method, the openings 121 are extended into the substrate 13. For example, a second selective etch may be performed on the substrate 13 to extend one or more openings 121 into the substrate 13. This may be referred to as a via etch of a first via.
图35示出了在第二示例性方法的另一个步骤中，移除抗蚀剂101，用保护层131覆盖填充材料311的部分，以防止在后续步骤中移除填充材料311的该部分。当前步骤可以称为块图案化。35 shows that in another step of the second exemplary method, the resist 101 is removed and a portion of the filling material 311 is covered with a protective layer 131 to prevent the portion of the filling material 311 from being removed in a subsequent step. The current step may be referred to as block patterning.
图36示出了在第二示例性方法的另一个步骤中，移除填充材料311以重新打开第一间隙51。例如，可以选择性地蚀刻填充材料311。然后移除保护层131，并保留先前覆盖的填充材料311。36 shows that in another step of the second exemplary method, the filling material 311 is removed to reopen the first gap 51. For example, the filling material 311 can be selectively etched. The protective layer 131 is then removed, and the previously covered filling material 311 remains.
图37示出了在第二示例性方法的另一个步骤中，将第一金属材料61沉积到重新打开的第一间隙51中。将第一金属材料61沉积到重新打开的第一间隙51中包括将第一金属材料61沉积到延伸到衬底13中的开口121中，以形成一个或多个第一过孔。然后，可以执行类似CMP的平坦化。37 shows that in another step of the second exemplary method, a first metal material 61 is deposited into the reopened first gap 51. Depositing the first metal material 61 into the reopened first gap 51 includes depositing the first metal material 61 into the opening 121 extending into the substrate 13 to form one or more first vias. Then, planarization like CMP may be performed.
图38示出了在第二示例性方法的另一个步骤中，在衬底13的方向上凹陷在第一间隙51中的第一金属材料61。FIG. 38 shows, in a further step of the second exemplary method, first metal material 61 which is recessed in first gap 51 in the direction of substrate 13 .
图39示出了在第二示例性方法的另一个步骤中，将第一硬掩模材料171沉积到凹陷的第一金属材料61中。FIG. 39 shows that in another step of the second exemplary method, a first hard mask material 171 is deposited into the recessed first metal material 61 .
图40示出了在第二示例性方法的另一个步骤中，通过选择性地移除第一间隔件21和第二间隔件22来形成多个第二间隙71。这可以称为间隔拉动。40 shows that in another step of the second exemplary method, a plurality of second gaps 71 are formed by selectively removing the first spacers 21 and the second spacers 22. This may be referred to as spacer pulling.
图41示出了在第二示例性方法的另一个步骤中，将第一介电材料81沉积到第二间隙71中。此外，在沉积到第二间隙71中的第一介电材料81中形成多个沟槽82。例如，对介电材料81执行选择性蚀刻可以形成一个或多个沟槽82。41 shows that in another step of the second exemplary method, a first dielectric material 81 is deposited into the second gap 71. In addition, a plurality of trenches 82 are formed in the first dielectric material 81 deposited into the second gap 71. For example, selective etching of the dielectric material 81 may form the one or more trenches 82.
图42示出了在第二示例性方法的另一个步骤中，将填充材料201沉积到多个沟槽82中。然后执行进一步的光刻图案化。该光刻图案化可以包括在中间集成器件的表面上涂抹抗蚀剂101，通过在抗蚀剂101中形成掩模开口42，暴露一个或多个填充有填充物材料201的沟槽82。42 shows that in another step of the second exemplary method, a filling material 201 is deposited into a plurality of trenches 82. Then further photolithographic patterning is performed. The photolithographic patterning may include applying a resist 101 on the surface of the intermediate integrated device, exposing one or more trenches 82 filled with the filling material 201 by forming a mask opening 42 in the resist 101.
图43示出了在第二示例性方法的另一个步骤中，可以在一个或多个暴露的沟槽82中对填充材料201执行第一选择性蚀刻，以从这些一个或多个沟槽82中移除填充材料202。FIG. 43 shows that in another step of the second exemplary method, a first selective etching may be performed on the filling material 201 in the one or more exposed trenches 82 to remove the filling material 202 from the one or more trenches 82 .
图44示出了在第二示例性方法的另一个步骤中，可以对暴露的一个或多个沟槽82中的介电材料81执行第二选择性蚀刻，以将一个或多个沟槽82延伸穿过介电材料81并进入衬底13中。这可以称为第二过孔的过孔蚀刻。44 shows that in another step of the second exemplary method, a second selective etch may be performed on the dielectric material 81 in the exposed one or more trenches 82 to extend the one or more trenches 82 through the dielectric material 81 and into the substrate 13. This may be referred to as a via etch of a second via.
图45示出了在第二示例性方法的另一个步骤中，移除抗蚀剂101，在填充有填充材料201的一个或多个沟槽82的部分上提供第三介电材料451。FIG. 45 shows that in another step of the second exemplary method, the resist 101 is removed and a third dielectric material 451 is provided on the portion of the one or more trenches 82 filled with the filling material 201 .
图46示出了在第二示例性方法的另一个步骤中，移除填充材料201。然而，在覆盖有第三介电材料451的填充材料201的一个或多个沟槽82的部分中，防止移除填充材料201，并且在移除第三介电材料451之后仍然保留填充材料201。46 shows that in another step of the second exemplary method, the filling material 201 is removed. However, in the portion of the one or more trenches 82 covered with the filling material 201 of the third dielectric material 451, the filling material 201 is prevented from being removed, and the filling material 201 still remains after the third dielectric material 451 is removed.
图47示出了在第二示例性方法的另一个步骤中，将第二金属材料91沉积到沟槽82中。防止将第二金属材料91沉积到沟槽82中残留有填充材料201的部分。将第二金属材料91沉积到延伸到衬底13中的沟槽82中，以形成第二过孔。然后，可以执行CMP。47 shows that in another step of the second exemplary method, a second metal material 91 is deposited into the trench 82. The second metal material 91 is prevented from being deposited into the portion of the trench 82 where the filling material 201 remains. The second metal material 91 is deposited into the trench 82 extending into the substrate 13 to form a second via. Then, CMP may be performed.
图48示出了在第二示例性方法的另一个步骤中，可以在衬底13的方向上凹陷暴露的第二金属材料91。FIG. 48 shows that in a further step of the second exemplary method, the exposed second metal material 91 may be recessed in the direction of the substrate 13 .
图49示出了在第二示例性方法的另一个步骤中，将第二硬掩模材料291沉积到凹陷的第二金属材料91中。FIG. 49 shows that in another step of the second exemplary method, a second hard mask material 291 is deposited into the recessed second metal material 91 .
上述所有方法都是分别参照图1至图9、图10至图29和图30至图49描述的，其中第一间隔件21和第二间隔件22的材料与第三间隔件31和第四间隔件33的材料是不同的材料。第一间隔件21和第二间隔件22由相同的材料制成。第三间隔件31和第四间隔件32也可以由相同的材料制成。间隔件21、间隔件22、间隔件31、间隔件32可以分别由氧化物(例如，氧化硅或氧化钛)或氮化物(例如，氮化硅)或硅锗或其它合适的间隔件材料制成。All of the above methods are described with reference to FIGS. 1 to 9, 10 to 29, and 30 to 49, respectively, wherein the materials of the first spacer 21 and the second spacer 22 are different from the materials of the third spacer 31 and the fourth spacer 33. The first spacer 21 and the second spacer 22 are made of the same material. The third spacer 31 and the fourth spacer 32 may also be made of the same material. The spacer 21, the spacer 22, the spacer 31, and the spacer 32 may be made of oxide (e.g., silicon oxide or titanium oxide) or nitride (e.g., silicon nitride) or silicon germanium or other suitable spacer materials, respectively.
上述所有方法都是分别参照图1至图9、图10至图29和图30至图49描述的，其中第一金属材料和第二金属材料是不同的材料。例如，第一金属可以包括以下至少一种：钌、铜、钼、钴和钨。例如，第二金属材料可以包括以下至少一种：钌、铜、钼、钴和钨。All of the above methods are described with reference to FIGS. 1 to 9, 10 to 29, and 30 to 49, respectively, wherein the first metal material and the second metal material are different materials. For example, the first metal may include at least one of ruthenium, copper, molybdenum, cobalt, and tungsten. For example, the second metal material may include at least one of ruthenium, copper, molybdenum, cobalt, and tungsten.
上述所有方法都是分别参照图1至图9、图10至图29和图30至图49描述的，其中衬底13包括以下至少一种个：MOL层和BEOL层。此外，第一介电材料81可以包括氮化硅和/或可以包括用于MOL层的电介质。All the above methods are described with reference to Figures 1 to 9, 10 to 29 and 30 to 49, respectively, wherein the substrate 13 includes at least one of the following: an MOL layer and a BEOL layer. In addition, the first dielectric material 81 may include silicon nitride and/or may include a dielectric for the MOL layer.
上述所有方法都是分别参照图1至图9、图10至图29和图30至图49描述的，其中衬底13包括一个或多个集成电路；此外，第一结构11和/或第二结构12可以是衬底13中的至少一个集成电路的电源轨。All of the above methods are described with reference to Figures 1 to 9, 10 to 29 and 30 to 49, respectively, wherein the substrate 13 includes one or more integrated circuits; in addition, the first structure 11 and/or the second structure 12 can be a power rail for at least one integrated circuit in the substrate 13.
本发明已结合各种实施例作为示例并结合实现方式进行描述。然而，根据对附图、本发明和独立权利要求的研究，本领域技术人员在实施所要求保护的主题时，能够理解和实现其它变型。在权利要求书以及说明书中，词语“包括”不排除其它元件或步骤，且不定冠词“一个”不排除多个。单个元素或其它单元可以满足权利要求书中描述的若干实体或项目的功能。在互不相同的从属权利要求中列举某些措施并不表示这些措施的组合不能在有利的实现方式中使用。The invention has been described in conjunction with various embodiments as examples and in conjunction with implementations. However, from a study of the drawings, the invention and the independent claims, other variations will be understood and implemented by a person skilled in the art in implementing the claimed subject matter. In the claims and in the specification, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. The enumeration of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.
Claims (18)
1. A metal integration method (10) for manufacturing an integrated device, the method (10) comprising:
-forming a first structure (11) and a second structure (12) from a common layer on a substrate (13), wherein the first structure (11) and the second metal structure (12) are separated from each other along a first direction (x) and each extend to a second direction (z);
-forming a first spacer (21) and a second spacer (22) on the substrate (13), wherein the first spacer (21) and the second spacer (22) each extend to the second direction (z), the first spacer (21) lining the first structure (11) on both sides of the first structure (11), the second spacer (22) lining the second structure (12) on both sides of the second structure (12);
-forming third and fourth spacers (31, 32) on the substrate (13), wherein the third and fourth spacers (31, 32) each extend to the second direction (z), the third spacer (31) lining the first spacer (21) on both sides of the first spacer (21), the fourth spacer (32) lining the second spacer (22) on both sides of the second spacer (22);
-forming a fifth spacer (41) between the third spacer (31) and the fourth spacer (32);
-forming a plurality of first gaps (51) by selectively removing the third spacers (31), the fourth spacers (32), the first structures (11) and the second structures (12);
-depositing a first metallic material (61) into the first gap (51);
-forming a plurality of second gaps (71) by selectively removing the first spacers (21) and the second spacers (22);
-depositing a first dielectric material (81) into the second gap (71);
-forming a plurality of trenches (82) in the first dielectric material (81) in the second gap (7);
a second metallic material (91) is deposited into the trench (82).
2. The method (10) of claim 1, further comprising, after selectively removing the third spacer (31), the fourth spacer (32), the first structure (11), and the second structure (12):
depositing a first filler material (311) into the first gap (51);
-removing the first filling material (311) to reopen the first gap (51);
Wherein the first metallic material (61) is deposited into the reopened first gap (51).
3. The method (10) according to claim 1 or 2, further comprising, prior to selectively removing the first spacer (21) and the second spacer (22):
-forming one or more openings (121) selectively in the third spacer (31), or in the fourth spacer (32), or in the first filler material (311), respectively;
-extending the opening (121) into the substrate (13);
wherein depositing the first metal material (61) into the first gap (51) comprises depositing the first metal material (61) into the opening (121) extending into the substrate (13) to form one or more first vias.
4. A method (10) according to any one of claims 1 to 3, characterized by, before depositing the second metallic material (91) into the trench (82), further comprising:
-extending one or more of said trenches (82) through said first dielectric material (81) and into said substrate (13);
Wherein depositing the second metallic material (91) into the trench (82) comprises depositing the second metallic material (91) into the trench (82) extending into the substrate (13) to form one or more second vias.
5. The method (10) according to claim 3 or 4, characterized in that the one or more openings (121) are formed in the third spacer (31), or in the fourth spacer (32), or in the first filling material (311) by:
Photoetching and patterning;
-performing a first selective etch of the third spacer (31) or the fourth spacer (32) or the first filling material (311) to form the one or more openings (121);
a second selective etch is performed on the substrate (13) to extend the one or more openings (121) into the substrate (13).
6. The method (10) according to any one of claims 2 to 5, further comprising, prior to selectively removing the third spacer (31) or the fourth spacer (32), or prior to removing the first filler material (311):
-covering a portion of the third spacer (31) or the fourth spacer (32) or the first filler material (311) with a protective layer (131) to prevent the portion of the third spacer (31) or the fourth spacer (32) or the first filler material (311) from being removed.
7. The method (10) according to any one of claims 1 to 6, further comprising, prior to selectively removing the first spacer (21) and the second spacer (22):
-recessing the first metallic material (61) in the first gap (51);
a first hard mask material (171) is deposited into the first gap (51) covering the recessed first metal material (61).
8. The method (10) according to any one of claims 4 to 7, wherein the one or more trenches (82) extend into the substrate (13) by:
depositing a second fill material (201) into the plurality of trenches (82);
Photoetching and patterning;
-performing a first selective etch of the second filling material (201) in the one or more trenches (82);
-performing a second selective etch on the dielectric material (81) to extend the one or more trenches (82) through the dielectric material (81) and into the substrate (13);
-removing the second filling material (201).
9. The method (10) according to any one of claims 1 to 8, further comprising, after depositing the second metallic material (91) into the trench (82):
selectively removing portions of the second metallic material (91);
A second dielectric material (271) is deposited to a location where the second metal material (91) is selectively removed.
10. The method (10) of claim 9, wherein the selectively removing the portion of the second metallic material (91) includes:
Lithographically patterning to expose only the portions of the second metal material (91);
A selective metal etch is performed on the exposed second metal material (91).
11. The method (10) according to any one of claims 1 to 8, comprising, prior to depositing the second metallic material (91) into the trench (82):
a third dielectric material (451) is formed in a portion of the trench (82) to prevent deposition of the second metal material (91) into the portion of the trench (82).
12. The method (10) according to any one of claims 9 or 11, further comprising:
Recessing the exposed second metal material (91);
A second hard mask material (291) is deposited into the recessed second metal material (91).
13. The method (10) according to any one of claims 1 to 12, characterized in that:
The material of the first spacer (21) and the second spacer (22) is different from the material of the third spacer (31) and the fourth spacer (32), and/or
The first metal material (61) and the second metal material (91) are different materials.
14. The method (10) according to any one of claims 1 to 13, characterized in that:
The first metal material (61) and/or the second metal material (91) comprises at least one of ruthenium, copper, molybdenum, cobalt and tungsten.
15. The method (10) according to any one of claims 1 to 14, wherein:
The substrate (13) includes at least one of a middle of line (MOL) layer and a back end of line (BEOL) layer.
16. The method (10) according to any one of claims 1 to 15, wherein:
the first dielectric material (81) comprises silicon nitride and/or a dielectric for the MOL layer.
17. The method (10) according to any one of claims 1 to 16, wherein:
-the substrate (13) comprises one or more integrated circuits;
The first structure (11) and/or the second structure (12) are power rails of at least one integrated circuit in the substrate (13).
18. An integrated device, characterized in that it is obtainable by a method (10) according to any one of claims 1 to 17.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2022/097621 WO2023236103A1 (en) | 2022-06-08 | 2022-06-08 | Method of metal integration for fabricating integrated device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119301758A true CN119301758A (en) | 2025-01-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280096666.4A Pending CN119301758A (en) | 2022-06-08 | 2022-06-08 | A metal integration method for manufacturing integrated devices |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN119301758A (en) |
| WO (1) | WO2023236103A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429123B1 (en) * | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
| US7879728B2 (en) * | 2008-01-23 | 2011-02-01 | International Business Machines Corporation | Sub-lithographic printing method |
| CN103928312B (en) * | 2013-01-10 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of pattern |
| US10079180B1 (en) * | 2017-03-14 | 2018-09-18 | United Microelectronics Corp. | Method of forming a semiconductor device |
| US11373880B2 (en) * | 2020-09-22 | 2022-06-28 | International Business Machines Corporation | Creating different width lines and spaces in a metal layer |
-
2022
- 2022-06-08 WO PCT/CN2022/097621 patent/WO2023236103A1/en not_active Ceased
- 2022-06-08 CN CN202280096666.4A patent/CN119301758A/en active Pending
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| Publication number | Publication date |
|---|---|
| WO2023236103A1 (en) | 2023-12-14 |
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