Ultra-low gate count & resources and ultra-low latency performances are the key differentiators. Our products also have excellent timing margin and a rich set of standard and advanced features. They are based on a unified architecture where all rates and options are supported using a unique Verilog source code and UVM environment.
All our IP cores are extensively verified in simulations using a Universal Verification Environment (UVM) methodology with a full suite of tests that ensures interoperability with the IEEE 802.3 standard. The products are also ported on FPGA platforms to test performances and verify interoperability with standard network testing appliance equipment.