Week 3: EE 292P Atoms, Bits, and the National Interest — The Semiconductor Technology Pt. 2

Stanford EE professor, TSMC vet, and Hanover venture partner Dr. Ali Keshavarzi and Hanover founding partner Joe Malchow created EE 292P and are teaching it at Stanford winter quarter 2026. Called “Atoms, Bits, and the National Interest,” or ABNI, we are attempting to trace the build-up of national power resulting from the growth of the semiconductor industry — from transistor physics through to great power competition.

We’re bringing in leaders from key companies in tooling, foundry, design, logic, memory, power electronics, AI applications, and other fields including economics and law.

This week we were honored to have Professor Mark Lundstrom join us. The Scifres Distinguished Professor of Electrical and Computer Engineering and former Dean of Engineering of Purdue, Prof. Lundstrom has been called the “Chief Semiconductor Officer” of Purdue. He is an expert on MOSFET scaling and the author of seminal books on transistor physics, including Transistors! and Essential Semiconductor Physics. If you are following our course and never studied how chips themselves work, these books are where to start.

We were also joined by our friend Gaurav Thareja, head of logic and memory process integration at Applied Materials, to discuss the tooling and manufacturing hurdles on the way to a trillion-transistor device.

Week 3— The Semiconductor Technology — Pt. 2

Lecturer: Mark Lundstrom (Purdue University)
Guest: Gaurav Thareja (Applied Materials; Adjunct Professor, Stanford)

Tuesday, January 20, 2026
Lane 200–205
Stanford, Calif.

Resources:

EE 292P Week 3 — Lundstrom MOSFETs Lecture Deck 1, Intro [PDF]
EE 292P Week 3 — Lundstrom MOSFETs Lecture Deck 3, Energy Band [PDF]
EE 292P Week 3 – Thareja — Enabling The Trillion Transistor Era [PDF]

Session Overview

Week 3 provided a comprehensive examination of transistor physics and the semiconductor manufacturing roadmap. The session featured two distinct but complementary perspectives: Prof. Mark Lundstrom’s treatment of the essential physics underlying transistor operation, and Gaurav Thareja’s industry view of advanced manufacturing technology enabling the trillion-transistor era.

Context from Week 2: The previous session covered ferroelectric materials and their potential to reduce effective oxide thickness by 2 angstroms while improving reliability. This week builds on that foundation by examining the fundamental physics of how transistors work and the architectural innovations driving continued scaling.

Part 1: Essential Physics of Transistors (Prof. Mark Lundstrom)

Historical Context

The field effect transistor was first patented by Julius Lilienfeld in 1925, making 2025 the 100th anniversary of the FET concept. However, the device couldn’t be built at the time due to surface state problems. The Bell Labs team attempting to build a FET in 1947 stumbled upon the bipolar transistor instead.

The breakthrough came in 1959 when Mohamed Atalla (a Purdue mechanical engineering PhD) and Dawon Kahng at Bell Labs successfully passivated the silicon surface with silicon dioxide, enabling the first working MOSFET. This device became “the most important invention of the 20th century.”

The Central Tool: Energy Band Diagrams

Kroemer’s Lemma of Proven Ignorance: “If in discussing a semiconductor problem, you cannot draw an energy band diagram, this shows that you don’t know what you’re talking about.”

Corollary: “If you can draw an energy band diagram, but you don’t, your audience won’t know what you’re talking about.”

Energy band diagrams have been the semiconductor physicist’s primary conceptual tool since 1948, when William Shockley used them to explain the bipolar transistor. They reveal:

● How transistors control current flow

● Why devices have their characteristic IV curves

● What limits device scaling

● Where electrostatic control breaks down

Basic energy band concepts:

● At low temperatures, all states below the valence band are filled with electrons

● All states above the conduction band are empty

● The gap between valence and conduction bands contains no states

● Key principle: A positive voltage lowers electron energy (pulls bands down)

How a MOSFET Works: Barrier Control

Prof. Lundstrom’s central insight: Transistors work by controlling an energy barrier between source and drain.

The mechanism:

1. Source and drain are heavily doped n-type regions (for NMOS) with excess electrons

2. The channel region between them is p-type with few free electrons

3. Applying positive gate voltage creates an electric field that pulls the bands down

4. When bands are pulled down enough, electrons can flow from source to drain

5. The gate voltage controls the barrier height, which exponentially affects current

Why this matters: Once you understand barrier control, the entire IV characteristic makes sense. The transistor is fundamentally an electronically-controlled energy barrier.

Critical Device Metrics

On-Current (ION)

Definition: Current when device is fully on Measurement condition: VGS = VDS = VDD Units: μA/μm (normalized to device width) Typical value: 1.6 μA/μm for 32nm PMOS

What it determines:

● Switching speed of digital circuits

● Drive strength for charging/discharging capacitive loads

● Maximum operating frequency

Physical factors:

● Barrier height when VGS = VDD

● Carrier mobility in the channel

● Effective channel width

● Source/drain contact resistance

Off-Current (IOFF)

Definition: Leakage current when device should be off Measurement condition: VGS = 0, VDS = VDD Units: A/μm Typical value: 10⁻⁷ A/μm for 32nm PMOS

What it determines:

● Static power consumption

● Battery life in mobile devices

● Thermal management requirements

● Standby power in data centers

Physical origin: Even with zero gate voltage, some electrons have enough thermal energy to surmount or tunnel through the barrier.

Subthreshold Swing (SS)

Definition: mV of gate voltage increase needed to increase drain current by 10× Units: mV/decade Fundamental limit: 60 mV/decade at T = 300K Typical value: 105 mV/decade for 32nm PMOS

The formula:

SS = (∂log₁₀(ID) / ∂VGS)⁻¹

Why 60 mV/decade is fundamental: This limit arises from the Boltzmann distribution of electron energies at a given temperature. The barrier height must change by kT/q to change the current by e (2.718×). Converting to decade and mV:

SS = (kT/q) × ln(10) = 60 mV/decade at 300K

Why this matters:

● Determines how sharply the transistor switches

● Sets minimum VDD for acceptable ION/IOFF ratio

● Cannot be improved in conventional MOSFETs without cooling

● Steep-slope devices (tunnel FETs, ferroelectric FETs) aim to beat this limit

DIBL (Drain-Induced Barrier Lowering)

Definition: Change in gate voltage needed to maintain constant drain current when drain voltage changes Units: mV/V Typical value: 130 mV/V for 32nm PMOS

The formula:

DIBL = ∂VGS/∂VDS|ID = constant

Physical mechanism:

● The drain voltage creates an electric field in the channel

● This field lowers the source-to-channel barrier

● The gate loses some control over the barrier height

● Higher drain voltage = lower barrier = more current (even at fixed VGS)

What it indicates:

● Quality of electrostatic control

● Severity of short-channel effects

● How well the gate “owns” the channel

● Susceptibility to drain voltage variations

Related effects:

● Finite output resistance (should be infinite)

● Threshold voltage dependence on VDS

● Subthreshold slope degradation

Output Resistance (ro)

Definition: Inverse of drain current change with drain voltage Units: Ω-μm Ideal value: Infinite Typical value: 2 kΩ-μm for 32nm PMOS

The formula:

ro = (dID/dVDS)⁻¹ at constant VGS

What it determines:

● Voltage gain in analog circuits

● Sensitivity to power supply variations

● Signal integrity in mixed-signal designs

Transconductance (gm)

Definition: Change in drain current per unit change in gate voltage Units: mS/μm Typical value: 2.7 mS/μm for 32nm PMOS

The formula:

gm = ∂ID/∂VGS at constant VDS

What it determines:

● Voltage gain (gm × ro)

● Switching speed

● Analog amplifier performance

The ION-IOFF Tradeoff: A Fundamental Constraint

The MOSFET physics creates an unavoidable tension:

ION scaling: ION ~ (VDD — VT)

● Linear relationship with overdrive voltage

● To increase ION, increase VDD or decrease VT

IOFF scaling: IOFF ~ exp[–qVT/kBT]

● Exponential relationship with threshold voltage

● Lowering VT increases IOFF exponentially

The dilemma:

● To reduce power, we want to lower VDD

● To maintain ION with lower VDD, we must lower VT

● But lowering VT exponentially increases IOFF and static power

The consequence: This tradeoff sets a practical lower limit of VDD ~ 1V for conventional CMOS. Going below 0.7V results in unacceptable leakage power, regardless of transistor design.

Example calculation:

● Start: VDD = 1.0V, VT = 0.4V, IOFF = 10⁻⁷ A/μm

● Reduce VT by 100mV to maintain ION with lower VDD

● New IOFF = 10⁻⁷ × exp(0.1V × 38.7/V) ≈ 4.8 × 10⁻⁶ A/μm

● Result: 48× increase in leakage power

Transistor Physics: Key Parameters

The transistor delay formula:

Delay = CV/ID = CR

Where:

● C = capacitance being charged

● V = voltage swing

● ID = drive current

● R = effective resistance

Drive current in saturation:

ID ≈ (Weff/Lg) × (μ/tox) × (VG — VT)²

Where:

● Weff = effective channel width

● Lg = gate length

● μ = carrier mobility

● tox = oxide thickness

● VG — VT = gate overdrive

Implications for scaling:

● Smaller Lg → higher ID (but worse short-channel effects)

● Thinner tox → higher ID (but gate leakage and reliability issues)

● Higher μ → higher ID (motivation for strained silicon, high-mobility channels)

● Lower VT → higher ID (but exponentially higher IOFF)

Scaling Limits: The Physics of “Game Over”

Quantum tunneling becomes the ultimate barrier to scaling:

The problem:

● As gate length shrinks below ~7nm, the barrier becomes thin enough for quantum tunneling

● Electrons can tunnel through the barrier even when the gate voltage is zero

● No amount of gate control can fully turn the device off

● IOFF increases exponentially as the barrier thins

The timeline:

● ~7nm: Tunneling becomes measurable

● ~5nm: Tunneling contributes significantly to IOFF

● ~4nm: Tunneling dominates, device cannot be turned off

● Below 4nm: Fundamental physics limit reached

Why this is different: This is not an engineering challenge that can be solved with better materials or structures. It’s a hard quantum mechanical limit. The electron wavelength is comparable to the barrier width, and tunneling is inevitable.

N-channel vs. P-channel MOSFETs

Why both are needed: CMOS (Complementary MOS) uses both NMOS and PMOS together. When one is on, the other is off, enabling very low static power consumption.

Part 2: Semiconductor Manufacturing Roadmap (Gaurav Thareja, AMAT)

The Trillion Transistor Era

The semiconductor industry is entering unprecedented scale:

Scaling trends (TSMC/Stanford/IEEE Spectrum, March 2024):

● Chip-to-chip bond density using SoIC: 1.74× every 2 years

● Transistors per processor: 1.73× every 2 years

● Projected: 1 trillion transistors per chip by 2030

The AI era: Machine-generated data surpassed human-generated data in 2018. The semiconductor industry revenue is projected to reach $1 trillion by 2030, driven primarily by AI compute demand.

Technology Evolution: From Planar to 3D Stacking

The CMOS scaling timeline:

PPA improvements (Planar to 2nm GAA):

● Performance: 3.5× improvement

● Power: 6.0× reduction

● Area: 5.5× reduction

DTCO contribution: Design-Technology Co-Optimization contributes >50% of scaling benefits at advanced nodes, not just dimensional shrinking.

Why Gate-All-Around (GAA) Nanosheets?

GAA technology was adopted by all major manufacturers (Samsung, Intel, TSMC) for nodes beyond 3nm because it solves the fundamental electrostatic control problem.

The Scaling Challenge: DIBL and Short-Channel Effects

As transistors scale, several problems emerge:

FinFET scaling limitations:

The root cause: As the gate length shrinks, the gate electrode becomes less effective at controlling the channel potential. The drain voltage starts to influence the barrier — this is DIBL.

The GAA Solution: Complete Electrostatic Control

Structure: The gate completely surrounds the channel (all four sides), maximizing electrostatic control.

Benefits over FinFET:

Cell placement and speed optimization: GAA enables better cell placement and speed range optimization compared to fixed-width FinFETs.

Industry Implementation (VLSI 2023, IEDM 2023)

Samsung (VLSI 2023):

● Multi-bridge channel FET (MBCFET)

● Production at 3nm node

● Nanosheet width tunability demonstrated

Intel (VLSI 2020):

● RibbonFET (Intel’s GAA branding)

● Nanoribbon structure

● Planned for Intel 20A (2nm class)

TSMC (ISSCC 2021):

● Demonstrated at 3nm

● Full wafer-scale production capability

● Superior performance per area vs. FinFET

CFET: The Next Architectural Leap

Complementary FET represents the next major density improvement by stacking NMOS on top of PMOS within the same footprint.

Density benefit: 1.5–2× transistor density compared to side-by-side GAA

Why it’s hard:

● Requires processing bottom tier, then building top tier without damaging bottom

● Thermal budget constraints (can’t use high-temperature processes twice)

● Alignment between top and bottom tiers

● Contact formation to both tiers

● Middle dielectric isolation (MDI) between NMOS and PMOS

Industry Progress (IEDM 2023)

Intel:

● Achievement: First CFET inverter circuits

● Innovation: Backside Direct Contact (BSCON) + Power Via

● Structure: FS WAC contact connecting top and bottom EPI

● Status: Proof of concept

TSMC:

● Achievement: 48nm CPP CFET with MDI

● Performance: Single NMOS & PMOS >1mA/μA, >90% device survival rate

● Structure: Middle dielectric isolation between tiers

● Status: Development

Samsung:

● Achievement: CFET prototypes at 48/45nm CPP

● Structure: 2N/2P nanosheet configuration

● Findings: S/D isolation critical to avoid leakage; stacked nFET/pFET preferable

● Status: Early development

Timeline: 10–15 years to production (2035–2040)

Backside Power Distribution Network (BSPDN)

The Frontside Power Problem

Current architecture: Both power and signal routed on the front side of the wafer, through 12–15 metal layers.

The problem:

● Large IR drop across many metal levels (~50% voltage drop)

● Each metal level adds resistance

● Total resistance = RM1 + RM2 + … + RM13

● Excessive IR drop creates reliability issues

● Limits ability to reduce VDD

Quantification: With 12+ metal levels, the cumulative resistance creates a 50% voltage drop from package to transistor.

The BSPDN Solution

Architecture change: Separate power and signal routing

● Front side: Signal lines only (reduced congestion)

● Back side: Power delivery through backside contacts

● Result: Shorter, lower-resistance power path

Benefits:

Implementation Approaches

Process flow for Direct Backside Contact:

6. Build transistors and front-side interconnects

7. Bond to carrier wafer

8. Flip wafer and thin from backside (extreme wafer thinning to ~500nm)

9. Create backside isolation

10. Form low-temperature backside contacts (DBC)

11. Build backside interconnect

Challenge: Extreme wafer thinning requires new handling and processing techniques. Wafer must be thinned to ~500nm (vs. 775μm starting thickness) to reach transistors from backside.

Materials Complexity: The Atomic Era

Then (early 2000s): ~5–10 materials

● Si substrate

● SiO₂, SiN dielectrics

● Al, Cu, W, Ti metals

● TiN, TaN barriers

Today (2025): ~25 materials in >100 combinations

● Channels: Si, SiGe (strained), SiC

● Gate dielectrics: HfO₂, ZrO₂, TaOx, ferroelectric superlattices

● Work function metals: N-type and P-type specific metals

● Interconnects: Cu, Co, Ru, low-resistance metals

● Barriers: TiN, TaN, TaAlN, TiAlN, metal alloys

● Low-k dielectrics: SiOC, flowable oxides, air gaps

Tomorrow (2030+): Atomic-level engineering

● 2D semiconductors: Graphene, MoS₂, WSe₂, CNT

● Alternative channels: III-V (InGaAs), Ge, 2D materials

● New memory materials: GST (phase change), IZO (selector)

● Advanced interconnects: Ruthenium, topological materials

● Ferroelectric materials: HfZrO₂ superlattices for negative capacitance

The atomic reality: Modern transistors have layers that are 1–2nm thick — just 3–7 atomic layers. At this scale:

● Every atomic layer matters

● Every interface matters

● Atomic-level precision is required

● Traditional bulk material properties no longer apply

Visualization: A modern GAA nanosheet has >5 different materials in the gate stack alone, each 1–2nm thick, requiring atomic layer deposition (ALD) with single-atom precision.

Manufacturing: 3,000 Steps to a Chip

Process complexity: A state-of-the-art chip requires >3,000 individual process steps.

Applied Materials’ Integrated Materials Solutions: 7 steps in vacuum for copper barrier seed (CuBS) process — unique capability enabling better interfaces and fewer defects.

The Yield Challenge

Historical reality: Best yields were 95–99% for mature processes.

Current reality: Modern advanced nodes achieve 30–60% yield.

The yield curve:

● R&D phase: 10–30% yield (learning, debugging)

● Transfer/Ramp: 30–60% yield (process optimization)

● High volume manufacturing: 60–90% yield (mature process)

Why yield matters:

● Each year of yield delay costs billions of dollars

● Expected 2-year development often becomes 4+ years

● Yield improvement is the difference between profit and loss

Example: 2nm technology expected in 2024 may not reach high-volume manufacturing until 2026 due to yield ramp.

Development cycle times:

● Full lot throughput: ~3 months (all 3,000+ steps)

● Short loop experiments: 1 day to 1 week (targeted step sequences)

● Innovation model: Rapid short-loop iteration with periodic full-lot validation

Inline metrology: Equipment placed every 10–20–30 steps to catch issues early, accelerating learning without waiting for full lot completion.

Sustainability: The Growing Environmental Cost

Per-wafer greenhouse gas emissions increase with each node:

Scope definitions:

● Scope 1: Direct emissions from fab facilities

● Scope 2: Emissions from energy supply to facilities

● Scope 3: Indirect emissions in value chain (materials, equipment)

Context: Data centers already account for 1% of global GHG emissions, and semiconductor manufacturing contributes significantly to this footprint.

The tradeoff: More advanced nodes enable more efficient computing (lower power per operation), but manufacturing them produces more emissions. Net benefit depends on use phase efficiency gains.

The PPACt + RYS Framework

Modern semiconductor development must optimize across eight dimensions:

The challenge: These metrics are in tension. Improving one often degrades another. Success requires finding the optimal balance for each application.

Physics of Transistor Performance

Transistor delay equation:

Delay = CV/ID = CR

Drive current equation:

ID ≈ (Weff/Lg) × (μ/tox) × (VG — VT)²

Scaling implications:

Variability impact: Speed is set by the slowest transistor. Reducing variability (σVT) improves average performance even without changing nominal device parameters.

Key Takeaways

1. Energy band diagrams are fundamental — They’re the essential conceptual tool for understanding transistor operation at a physical level. If you can’t draw the bands, you don’t understand the device.

2. Transistors work by barrier control — The gate voltage modulates an energy barrier between source and drain. This simple picture explains the entire IV characteristic.

3. 60 mV/decade is a hard thermodynamic limit — Subthreshold swing cannot go below this at room temperature in conventional MOSFETs. This limit arises from the Boltzmann distribution and cannot be engineered away.

4. DIBL is the key scaling challenge — As devices shrink, the drain voltage increasingly affects the source-channel barrier, degrading electrostatic control and increasing IOFF.

5. GAA solves the electrostatic control problem — Wrapping the gate completely around the channel (all four sides) maximizes gate control, enabling continued scaling to 2nm and beyond.

6. Quantum tunneling sets the ultimate limit — Below 4–7nm gate lengths, electrons tunnel through the barrier regardless of gate voltage. This is a hard quantum mechanical limit, not an engineering challenge.

7. CFET enables 1.5–2× density — Stacking NMOS on PMOS doubles transistor density but requires solving major integration challenges. Timeline: 10–15 years.

8. Backside power enables 20–30% area reduction — Separating power and signal routing eliminates front-side power rail congestion and reduces IR drop.

9. 15–20 years from materials discovery to production — New materials require extensive development, integration, and reliability validation. Innovation must start today for 2040 products.

10. Yield is the hidden cost of scaling — Modern advanced nodes achieve 30–60% yield vs. historical 95–99%. Each year of yield delay costs billions. Winning the PPACt race is worth billions to the ecosystem.

Looking Ahead

Next session (Week 4): Computing architecture with Tom Lee — moving from transistor physics to system-level efficiency, information extraction from AI models, and model efficiency metrics.

The big picture: We’re entering an era where physics, materials science, manufacturing, and architecture must co-evolve. The days of simple transistor scaling (shrink everything by 0.7×) are over. Future progress requires innovation across the entire stack:

● Device level: New materials (2D, III-V), new structures (CFET)

● Manufacturing: Atomic-level precision, backside processing

● Architecture: Heterogeneous integration, 3D stacking, chiplets

● System: Co-optimization of hardware and algorithms