Stanford EE professor, TSMC vet, and Hanover venture partner Dr. Ali Keshavarzi and Hanover founding partner Joe Malchow created EE 292P and are teaching it at Stanford winter quarter 2026. Called “Atoms, Bits, and the National Interest,” or ABNI, we are attempting to trace the build-up of national power resulting from the growth of the semiconductor industry — from transistor physics through to great power competition.
We’re bringing in leaders from key companies in tooling, foundry, design, logic, memory, power electronics, AI applications, and other fields including economics and law.
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Week 2 — The Semiconductor Technology — Pt. 1
Lecturer: Ali Keshavarzi (Adjunct Professor, Stanford EE)
Tuesday, January 13, 2026
Lane 200–205
Stanford, Calif.
Resources:
EE 292P Week 2 — Deck [PDF]
Course Overview & Context
This week marks the second lecture in the series, diving deep into semiconductors and materials after last week’s high-level introduction to the computing environment. The course follows a “staircase” approach:
1. Week 1: Technology environment and power/energy trends
2. Week 2 (today): Materials and semiconductor technology
3. Week 3: Transistor-level technology (with Mark Lundstrom from Purdue)
4. Week 4: Computing architectures and intelligence per watt metrics
5. Later weeks: Building back up to geoeconomics and geopolitics
Reading: The Economist (August 2023) — “All American Silicon” technology quarterly covering US, global, and China semiconductor competition.
The Power and Energy Crisis
Google’s Data Center Energy Consumption
The operational costs of computing are becoming unsustainable:
● 2019: 12.4 TWh (7% of global data center consumption)
● 2023: 24 TWh (2x increase from 2019)
● 2024: 30.8 TWh (27% year-over-year growth due to AI)
Cost Impact: At $0.30/kWh (Los Altos residential rate), Google’s 2024 electricity bill would be approximately $7 billion for data centers alone. Even with discounted commercial rates, this represents billions in operational expenses.
Context: Average US home uses 10,000 kWh per year. Google’s data centers consume the equivalent of millions of homes.
AI Training Costs: GPT-4 vs Grok 4
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Key Insight: While Grok 4 required 25x more compute than GPT-4, it only consumed 6x more energy. This suggests significant efficiency improvements from:
● Newer, more advanced chips
● Better training methodologies
● Improved model architectures
● More efficient data center infrastructure
The Efficiency Imperative: Computing efficiency is now a critical vector for both performance and cost management in AI development.
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Materials for Power Efficiency
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Cooling Limitations
The semiconductor industry faces a fundamental cooling constraint: ~100 watts per cm² is the maximum for air cooling without exotic heat transfer solutions.
As transistor density increases (more transistors per unit area through scaling), power density also increases. This creates a hard limit on chip performance unless better cooling or more efficient materials are employed.
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Wide Bandgap Semiconductors
Student responses identified several material systems for addressing power efficiency:
1. Gallium Nitride (GaN)
● High efficiency for power delivery
● Used in vehicle electrification and chargers
● Critical for power delivery to chips
2. Silicon Carbide (SiC)
● Another wide bandgap semiconductor
● Excellent for high-voltage, high-temperature applications
3. Diamond
● Ultra-high thermal conductivity (5× better than copper)
● Can be used for cooling pathways and heat transfer
● Potential as ultra-wide bandgap semiconductor if properly doped
● Research ongoing (including carbon nanotubes for similar purposes)
Industry Adoption Challenges
Case Study: Wolfspeed and Market Scale
The discussion revealed critical barriers to new material adoption:
● Small customer + small vendor = Partnership can work
● Large customer + small vendor = Doesn’t happen (not acceptable risk)
● Medium-scale success example: Navitas supplying GaN switches for utility-scale power conversion (~$200M program)
○ Game-changing for Navitas
○ Substantial but not transformative for Infineon
The Nvidia-Navitas Example: Despite announcements of Navitas supplying power units for Nvidia, actual deployment and revenue realization remain uncertain. Many industry announcements represent marketing rather than confirmed orders.
Key Insight: Technology readiness ≠ market adoption. The gap between prototype and high-volume manufacturing is enormous, requiring:
● Proven yield
● Demonstrated reliability
● Sufficient customer volume to justify production lines
● Multi-year design-in cycles
Ferroelectric Materials: A Case Study in Innovation Lag
Discovery and Potential
2011: Ferroelectric hafnium oxide (HfO₂) discovered at Namlab in Germany (in partnership with GlobalFoundries)
Significance: This is the same material system used in modern transistors as the high-K dielectric in high-K metal gate (HKMG) technology. The discovery that this material exhibits ferroelectricity opened new pathways for:
● Lower operating voltages
● Non-volatile memory
● Energy-efficient computing
2026: Still not mainstream after 15 years
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Why the Delay?
Micron’s 3D Non-Volatile Memory Example:
● Technology developed and qualified
● Shelved by Micron — not brought to market
● Reason: Strategic business decision (why sell a product that doesn’t require customers to return for upgrades?)
Technical Barriers:
● Yield challenges
● Reliability concerns
● Variability in manufacturing
● Integration complexity
Business Barriers:
● Insufficient volume to justify production lines
● First-mover risk in commodity markets
● Capital intensity of semiconductor manufacturing
● Competition from established technologies
Historical Parallel: High-K metal gate technology took nearly a decade from research to production (introduced at 45nm node in 2008).
Voltage Scaling and Transistor Physics
The Voltage Reduction Challenge
Current State: Most advanced nodes (3nm) operate at approximately 0.8–0.9V supply voltage, with future nodes targeting 0.75–0.8V.
Why Voltage Matters: Power consumption scales with V² (quadratically), so even small voltage reductions yield significant power savings.
The Leakage Current Problem
Historical Context: In the late 1990s/early 2000s, transistors were assumed to be perfect switches in CAD tools (zero off-current). As scaling continued, leakage became so severe that:
● 50% of chip power could be consumed by leakage
● Gordon Moore testified before Congress about the crisis
● Industry mobilized to address the fundamental physics problem
The Physics:
● Transistors are not delta functions (perfect on/off switches)
● There’s a transition region between on and off states
● At zero gate voltage, leakage current flows from source to drain
● As transistors shrink, controlling this leakage becomes harder
High-K Metal Gate Solution
The Problem: Silicon dioxide (SiO₂) gate dielectric couldn’t scale further without excessive leakage.
The Solution: Replace SiO₂ with high-K dielectric materials (hafnium oxide, HfO₂).
Why “High-K”?:
● K = dielectric constant
● Higher K = higher capacitance for same physical thickness
● Higher capacitance = better gate control of channel
● Better control = lower leakage when off, higher current when on
Structure (from gate down to channel):
6. Metal gate electrode
7. High-K dielectric (HfO₂)
8. Thin SiO₂ interface layer (critical for low defect density)
9. Silicon channel
Effective Oxide Thickness (EOT): The combination of SiO₂ interface and high-K layer creates equivalent electrical thickness much thinner than physical thickness, enabling continued scaling.
Introduction Timeline:
● Introduced at 45nm node (~2008)
● Now universal in advanced logic manufacturing
● Used in all modern transistor architectures (FinFET, gate-all-around, etc.)
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Where Ferroelectrics Fit
Ferroelectric materials would be integrated into this same gate stack structure, sitting where the high-K dielectric currently resides. The ferroelectric property could enable:
● Steeper switching characteristics (faster on/off transitions)
● Lower operating voltages
● Reduced power consumption
● Non-volatile logic capabilities
Industry Structure and Innovation
The Japan-US Memory Wars (1980s-90s)
Context: Japan aggressively competed with US companies in DRAM manufacturing, focusing on quality, defect reduction, and yield improvement.
Impact on Intel:
● Intel started as a DRAM memory company
● Japanese competition forced Intel to exit memory business
● Intel pivoted to microprocessors (CPUs)
● This pivot made Intel synonymous with computing processors
Lessons:
● First-to-scale markets are dangerous for component suppliers
● Inventory-based businesses face extreme risk in commodity markets
● Capital depth and willingness to sustain losses matter
● Industrial policy can play a significant role (debated whether Japan had formal policy)
Modern Parallels: AI Training Economics
The current AI training race mirrors the memory wars:
● First-to-scale market dynamics
● Massive capital requirements
● Risk of rapid demand shifts
● Inventory risk for component suppliers
Nvidia’s Strategy: Shifting from selling chips (inventory-based business) to leasing systems (service-based business) to reduce risk and increase value capture.
Who Brings Innovation to Market?
Key Questions for This Course:
● What is the role of small companies vs. large incumbents?
● How do startups scale in capital-intensive industries?
● What market conditions enable new materials/technologies?
● Is there room for new players when TSMC pivoted to CMOS decades ago?
The Chip Act Context: Recent US legislation aims to address these questions through industrial policy, but execution and fund distribution remain ongoing topics of analysis.
Key Takeaways
1. Power and energy are now primary constraints on computing performance and economics, not just technical curiosities.
2. Materials innovation is critical for addressing power challenges, but the path from discovery to deployment spans decades.
3. Business considerations often outweigh technical merit in determining which technologies reach the market.
4. Scale and capital requirements create high barriers to entry and adoption of new materials/technologies.
5. The semiconductor industry uses essentially the entire periodic table — materials science is fundamental to continued progress.
6. Voltage scaling remains the most powerful lever for power reduction, but requires materials innovation (high-K dielectrics, ferroelectrics) to enable.
7. Industry structure matters: The relationship between suppliers, customers, and scale determines what innovations succeed.
Looking Ahead
Next Week (January 20): Transistor-level technology with Mark Lundstrom (Purdue) and industry perspectives from Gaurav at Applied Materials.
January 27: Computing architectures and “intelligence per watt” metrics with researchers from the Hennessy/Re group.
Course Arc: Building from materials → transistors → computing → systems → geopolitics/geoeconomics of the semiconductor industry.