The Silicon Compiler Comes Back As An AI Agent Factory: Mead And Conway's 1980 Revolution, And IBM's $26 Chip-Design Swarm.
In the fall of 1978, Lynn Conway walked into a classroom at MIT carrying a textbook that did not exist yet.
It was a draft, printed on the laser printers at Xerox PARC. The title on the cover was "Introduction to VLSI Systems," and the authors were Carver Mead of Caltech and Conway herself. Her students were seniors and graduate students in electrical engineering and computer science. Most had never designed an integrated circuit. In those days a complex digital chip, in Conway's own words, required a team of "architects, logic designers, circuit designers, circuit layout designers, and process experts," and it took many months to a year to complete.
Conway planned to compress that into one semester. Half the term to learn the basics. Half the term to design a real chip. On December 5 and 6, 1978, the students' design files were sent over the Arpanet to Xerox PARC, merged into a single multi-project chip, turned into masks by Micro Mask, and fabricated at Hewlett-Packard's Deer Creek lab. By January 18, packaged chips were in the students' hands for testing, about a month after the final class meeting. One of those projects was a LISP microprocessor designed by a student named Guy Steele.
Hold that picture in your mind: a classroom of newcomers, a shared wafer, and working silicon in weeks. Forty-eight years later, IBM Research has published a result that rhymes with it almost perfectly, only this time the newcomers are AI agents, and the shared resource is a budget of one hundred ideas.
The Revolution On Paper
The Mead-Conway method was an act of translation. Chip design had been a craft held inside a few large companies and passed down through apprenticeship next to the fab. Mead and Conway wrote it down as a small set of clean, teachable rules: stick diagrams, scalable design rules, a symbolic layout language, and a structured way to move from system architecture down to the physics of the transistor.
Conway's own course description for MIT's 6.978 states the goal with charming directness. For computer science students the aim was "to take the mystery out of integrated circuit and system design." For electrical engineers it was to "take some of the mystery out of the design of complex integrated digital systems."
Conway's archive records that the final text was published by Addison-Wesley in the fall of 1979, "just in time for courses at many universities that fall." The book carries a 1980 copyright date, which is why it is usually cited as 1980, and why the date of the revolution is given as 1980 in this article's title.
MPC79: The Internet Becomes A Foundry
The MIT course worked. So Conway scaled it up. In the spring of 1979 she conceived of what her archive calls "a new type of internet-based implementation infrastructure," and that summer at PARC Alan Bell and Martin Newell built a software prototype of the "MPC System." In the fall of 1979, the project called MPC79 carried, by Conway's count, "a total of 82 VLSI system design projects from a total of 124 participating designers."
The designs came from courses at MIT, Caltech, Stanford, Illinois and Rochester, plus faculty and staff at several other universities. Scan the designer list and you find names that would shape the next forty years of computing: Jim Clark, who would found Silicon Graphics; Andy Bechtolsheim, a co-founder of Sun Microsystems; H. T. Kung of Carnegie-Mellon; and a three-person team from MIT listed as Ron Rivest, Len Adleman and Adi Shamir, the RSA trio, building a section of a multiplier. Conway writes that MPC79 helped carry the methods "into over 100 universities and scores of startup companies within just several years."
MOSIS: Shared Wafers For Everyone
Then the experiment became an institution. According to Conway's archive, the success of MPC79 "led to the transfer of that infrastructure to USC-ISI, where it became known as the 'MOSIS' service." DARPA's own history states that MOSIS "opened for business in January 1981," offering fast-turnaround, low-cost batches of custom chips, with "the pooling of several chip designs onto a single semiconductor wafer" as its key idea. Danny Cohen and George Lewicki of ISI described it at the Second Caltech Conference on VLSI in 1981 under a title that says everything: "MOSIS - The ARPA Silicon Broker." In 1985, DARPA and the National Science Foundation extended the service to universities teaching VLSI design courses.
The multi-project wafer is one of the quiet great ideas of the twentieth century. It turned the cost of a fabrication run, which no student could ever pay, into a slice that a class could share. It took the price of trying and divided it by everyone who wanted to try.
The First Silicon Compiler
One of Carver Mead's graduate students asked the next obvious question. If the rules of chip design were clean enough to teach a classroom, why not teach them to a program?
In 1979 Dave Johannsen published "Bristle Blocks: A Silicon Compiler." The paper appears in the Proceedings of the 16th Design Automation Conference, pages 310 to 313, and the History of Information project also records it being presented at the first Caltech Conference on VLSI in January 1979. It describes the term as the first use of "silicon compiler" for a software system "that takes a user's specifications and automatically generates an integrated circuit." Johannsen expanded the work into his 1981 Caltech PhD thesis, "Silicon Compilation." That same year, the History of Information project records, "Johannsen, Mead, and Edmund K. Cheng subsequently founded Silicon Compilers Inc. (SCI) in 1981."
So within about three years, the chain was complete. Mead and Conway lowered the price of knowing how. MOSIS lowered the price of fabrication. The silicon compiler lowered the price of layout. Each step took a gate that had been guarded by expertise or money and swung it open.
Remember the phrase silicon compiler. It just came back in a new form.
October 13, 2026: The AI Agent Factory
On October 13, 2026, IBM Research published a blog post titled "Making AI-driven chip design affordable with open agent factories and distributed inference at scale." It describes an "agent factory": a team of AI agents put to work exploring a hardware design, and it asks the question every engineering manager will now ask. What does that exploration cost?
High-level synthesis, or HLS, lets engineers describe hardware in C or C++ and lets a tool generate the lower-level register-transfer description. Engineers still face countless decisions about loop structure, parallelism, memory organization, dataflow and synthesis directives, and those decisions interact. As IBM puts it, "performing more calculations simultaneously helps only if the memory system can supply their inputs." The design space grows far too large for humans to explore exhaustively.
Ruchir Puri, IBM Fellow and IBM Research chief scientist, describes the factory this way: "An agent factory turns hardware optimization into a coordinated cycle of exploration: A coordinator agent directs parallel worker agents to develop and synthesize alternative designs within a defined search budget."
Here is the cast.
The coordinator. One agent plans the search and assigns optimization hypotheses. A hypothesis is a single idea to try, such as "reorganize how messages are stored" or "replace this sequential sum with a tree."
The four workers. Four parallel worker agents each take a hypothesis and modify the decoder implementation, then the change goes through synthesis.
The verifier. Puri again: "A verifier checks that the proposed improvements are valid, and the designs are ranked by latency and hardware resource use. Those results guide the next round of exploration, allowing the factory to refine its search as it discovers better designs."
The loop. Correctness checks and HLS results feed back into the next round. Each configuration received a budget of 100 hypotheses.
IBM gives two examples of what the agents actually found. One transformation "reorganized message storage so that the synthesis tool could identify independent memory accesses and execute more work in parallel." Another "replaced sequential reductions with tree structures that exposed parallel computation." These are exactly the kinds of moves a skilled human HLS engineer makes, discovered by agents and checked by a verifier.
The Target: A Decoder For Quantum Error Correction
IBM chose a hard and meaningful test. The target was Relay-BP, a quantum error correction decoding algorithm, for the [[144,12,12]] bivariate bicycle code.
Quantum computers make errors constantly. Measurements give clues about which errors happened, and a classical decoder must read those clues and infer the corrections fast enough to keep up. IBM calls doing that quickly, within practical hardware limits, "an essential part of building fault-tolerant quantum systems." Relay-BP repeats a message-passing computation that is inherently parallel, yet IBM notes that the baseline implementation's sparse graph representation and memory-access patterns make that parallelism hard for HLS tools to exploit. The agents had to keep the computation exactly the same while changing how the hardware performs it.
The Numbers: $26 And $299
IBM compared three configurations under the same 100-hypothesis budget: a proprietary frontier model as both coordinator and workers; an open frontier model in both roles; and a hybrid with a proprietary coordinator and open-model workers. The open model ran on premises.
The all-proprietary configuration reached the highest speedup, 204 times faster than the baseline design in high-level synthesis estimates, for about $299 of inference.
The all-open configuration reached a 52-times speedup for about $26 of inference, and it produced the smallest-area design in the study.
That is 11.5 times less money for the open setup. IBM summarizes the tradeoff in its own words: "Open and hybrid searches found useful compact designs, while the proprietary configuration more effectively converted additional resources into parallelism and lower latency." All three configurations found verified hardware improvements.
Here is the detail that surprised me most. The open search used more tokens, about 241 million against about 216 million for the proprietary search, and it still cost a fraction as much. The difference came from how those tokens were served.
llm-d: The Shared Wafer Of Inference
The open model was served through llm-d, an open-source, Kubernetes-native framework for distributed inference. IBM explains why that matters for this workload: "An agent factory repeatedly returns to much of the same information: source code, design constraints, earlier changes, and synthesis reports." llm-d's cache-aware routing sends requests toward servers that already hold that reusable context, and it separates prompt processing from token generation so each can get its own resources.
For the chip-design workload, IBM reports a prefix-cache hit rate of approximately 98 percent and a blended serving cost of about $0.11 per million tokens. And because the weights were open, the team could run the model on premises and keep control of the design files the agents handled.
Look at the shape of that. MOSIS pooled many chip designs onto one wafer so each designer paid for a slice. llm-d pools the shared context of many agent calls so each call pays for only what is new. The economics of 1981 and the economics of 2026 run on the same principle: share the expensive common part, and the price of trying collapses.
What IBM Says It Did Not Show
IBM is careful about limits, and so should we be.
Each configuration was evaluated in one search run, so IBM presents the results as a description of the searches it observed, with no claim of a universal ranking of models. The costs cover model inference only. IBM states that evaluation "will also need to account for synthesis and verification costs alongside inference." The speedups are high-level-synthesis estimates, which are an early-stage measure of a design. And more budget gave less than proportional gains: extending the all-open campaign from 100 to 200 hypotheses moved its speedup from 52 times to 60 times. IBM's word for those gains is "diminished."
The blog also refers to "the new paper" behind these results. At the time of writing I could not find a public link to that paper, so every number here comes from the IBM Research blog.
What It Means
For the whole history of hardware, the gate on invention has been the price of trying. In 1978 the price was knowledge, and Mead and Conway taught it away. In 1979 the price was a fabrication run, and the multi-project chip, then MOSIS, shared it out. In 1981 the price was hand layout, and the silicon compiler automated it.
In 2026 the price is exploration. An engineer can only test so many ideas in a week. An agent factory can test a hundred, check every one, and rank them, and IBM just showed one campaign for about the cost of a nice lunch.
IBM names the loop that follows: "Better hardware enables more capable AI, and more capable AI can help engineers develop better hardware." I would add one thing. This is the worst that loop will ever be.
I have spent a lifetime building hardware on a bench in my garage. The hardest part was never the soldering. It was the number of ideas I could afford to test.
[FIRST-PERSON, VERIFY] In the Zero-Human Company I run AI in roles: a CEO, an engineer, and regulators that check the work. IBM's factory is the same pattern aimed at silicon: one agent plans, several agents build, and one agent verifies before anything counts.
There is also a sovereignty lesson. The cheap configuration was the one with open weights, run on premises, with the design files kept in-house. The cheapest path and the most private path turned out to be the same path.
How You Could Try A Similar Agent Loop
Anyone can learn the pattern on a desktop. Here is a modest way to build a small coordinator, workers and verifier loop. Treat it as a learning exercise.
1. Pick a small, measurable target. Choose a short C function with a clear correct answer and a clear score: a sorting routine, a small matrix multiply, a checksum or a filter. If you want real hardware feedback, an open-source HLS tool such as PandA-Bambu can turn C into Verilog, and a simulator such as Verilator can check behavior. If hardware tools feel like too much, use run time on your own computer as the score. The loop teaches the same lesson.
2. Write the verifier first. Build a test harness with fixed inputs and known outputs, plus a script that compiles or synthesizes the candidate and reports a number, such as latency, cycles or area. The verifier is the heart of the factory. Any candidate that changes an output gets rejected, every time, with no exceptions.
3. Set a hypothesis budget. Decide up front how many ideas you will try, say 20. Log every hypothesis, the tokens it used and the score it earned. This is your own small version of IBM's 100-hypothesis budget, and it tells you your cost per idea.
4. Create the coordinator. Give one model the source code, the constraints and the history of past attempts with their scores. Ask it to propose a short list of distinct hypotheses, one sentence each, and to explain why each might help.
5. Create the workers. Run one worker per hypothesis, in parallel if your machine allows. Each worker gets the current best code and exactly one hypothesis, and returns a complete modified file. Keep each worker focused on its single idea.
6. Rank and repeat. Run every candidate through the verifier, keep the ones that pass, rank them by your score, and hand the ranked results back to the coordinator for the next round. Stop when the budget is spent.
7. Serve it efficiently. Run an open-weight model locally with a server that supports prefix caching, such as vLLM, and put the unchanging material (code, constraints, rules) at the start of every prompt so the cache can reuse it. Watch your cache hit rate. IBM's 98 percent figure shows why this matters: an agent loop rereads the same context over and over.
Keep everything versioned, keep a human look at the final winner, and never trust a speedup the verifier did not confirm. Begin small and record what you spend.
The Classroom Is Open Again
In 1978 Lynn Conway proved that a room of newcomers could design working chips if someone wrote down the rules and shared the wafer. In 1979 a graduate student proved a program could follow those rules. In 2026 IBM has shown that a team of agents can explore a real quantum-computing chip design, check its own work, and do it for about twenty-six dollars of inference.
The question now is who gets to run one. The answer, more and more, is anyone curious enough to try.
References
1. IBM Research, "Making AI-driven chip design affordable with open agent factories and distributed inference at scale," October 13, 2026.
https://research.ibm.com/blog/open-agent-factories-and-distributed-inference-for-chip-design
2. Lynn Conway, "The M.I.T. 1978 VLSI System Design Course," Lynn Conway's VLSI Archive, University of Michigan.
https://ai.eecs.umich.edu/people/conway/VLSI/MIT78/MIT78.html
3. Lynn Conway, "Drafts of the Mead-Conway textbook, Introduction to VLSI Systems," VLSI Archive.
https://ai.eecs.umich.edu/people/conway/VLSI/VLSIText/VLSIText.html
4. Lynn Conway, "MPC79 Designers and Their Projects," VLSI Archive.
https://ai.eecs.umich.edu/people/conway/VLSI/MPC79/ImpDoc/MPC79DesignersAndProjects.html
5. Carver Mead and Lynn Conway, Introduction to VLSI Systems, Addison-Wesley (copyright 1980; in print fall 1979 per Conway's archive).
6. DARPA, "MOSIS semiconductor service," Innovation Timeline.
https://www.darpa.mil/about/innovation-timeline/mosis-semiconductor-service
7. Danny Cohen and George Lewicki, "MOSIS - The ARPA Silicon Broker," Proceedings of the Second Caltech Conference on Very Large Scale Integration, 1981, pp. 29-44.
https://caltechconf.library.caltech.edu/219/
8. "Evolution of the MOSIS VLSI educational program," IEEE.
https://ieeexplore.ieee.org/document/994612
9. Dave Johannsen, "Bristle Blocks: A Silicon Compiler," Proceedings of the 16th Design Automation Conference, ACM, 1979, pp. 310-313.
https://bibtex.github.io/DAC-1979-Johannsen.html
10. David L. Johannsen, Silicon Compilation, PhD thesis, California Institute of Technology, 1981.
https://thesis.library.caltech.edu/4476/
11. History of Information, "David Johannsen Describes Silicon Compilation."
https://historyofinformation.com/detail.php?entryid=4362
12. llm-d, open-source distributed inference framework.