AAP: An Altruistic Processor

3.1.1. Assembler Notation

• [label:] opcode [arguments]

3.3.1. 16-bit Instructions of AAP

• Table 3.1 lists all the 16-bit ALU instructions, which have class 00;

• Table 3.2 lists all the 16-bit load/store instructions, which have class 01;

• Table 3.3 lists all the 16-bit branch/jump instructions, which have class 10; and

• Table 3.4 lists all the 16-bit miscellaneous instructions, which have class 11.

Table 3.1. 16-bit ALU instructions

Table 3.2. 16-bit load/store instructions

Table 3.3. 16-bit branch/jump instructions

Table 3.4. Miscellaneous 16-bit instructions

3.3.2. 32-bit Instructions of AAP

• Table 3.5 lists all the 32-bit ALU instructions, which have class 00xx;

• Table 3.6 lists all the 32-bit load/store instructions, which have class 01xx;

• Table 3.7 lists all the 32-bit branch/jump instructions, which have class 10xx; and

• There are no 32-bit instructions in the miscellaneous class, but if there were, they would have have class 11xx.

Table 3.5. 32-bit ALU instructions

Table 3.6. 32-bit load/store instructions

Table 3.7. 32-bit branch/jump instructions

3.4.1.  NOP: No Operation

• NOP R_d,I

• d ≤ 7

• I ≤ 63

• PC ← PC + 1

• This opcode may trigger side-effects in implementations, depending on the value of I, particularly when simulating (see Section 2.3).

  All implementations should use d = 0, I = 0 as the break instruction for debugging, which should halt the processor.

  All implementations should use d = 0, I = 1 as a true no-operation instruction.

  The rationale behind this decision is that in an erroneous program, the most likely value to be encountered as a random instruction is zero, which will stop the processor.

3.4.2.  ADD: Unsigned Add

• ADD R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a + R_b

  carry ← ( ( R_a + R_b ) ≥ 2¹⁶ ) ? 1 : 0

  PC ← PC + 1

3.4.3.  SUB: Unsigned Subtract

• SUB R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a - R_b

• carry ← ( R_b > R_a ) ? 1 : 0

• PC ← PC + 1

3.4.4.  AND: Bitwise AND

• AND R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a & R_b

• PC ← PC + 1

3.4.5.  OR: Bitwise OR

• OR R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a | R_b

• PC ← PC + 1

3.4.6.  XOR: Bitwise Exclusive OR

• XOR R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a ^ R_b

• PC ← PC + 1

3.4.7.  ASR: Arithmetic Shift Right

• ASR R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← ( R_a | ( carry << 16 ) ) >> R_b )

• carry ← 0

• PC ← PC + 1

• If R_b ≥ 17 the result in R_d will be zero.

• The carry flag is always cleared, even if a shift of zero is specified.

3.4.8.  LSL: Logical Shift Left

• LSL R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a << R_b

• PC ← PC + 1

• If R_b ≥ 16 the result in R_d will be zero.

3.4.9.  LSR: Logical Shift Right

• LSR R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• R_d ← R_a >> R_b

• PC ← PC + 1

• If R_b ≥ 16 the result in R_d will be zero.

3.4.10.  MOV: Move Register to Register

• MOV R_d,R_a

• a ≤ 7

• d ≤ 7

• R_d ← R_a

• PC ← PC + 1

3.4.11.  ADDI: Unsigned Add Immediate

• ADDI R_d,R_a,I

• a ≤ 7

• d ≤ 7

• I ≤ 7

• R_d ← R_a + I

  carry ← ( ( R_a + I ) ≥ 2¹⁶ ) ? 1 : 0

  PC ← PC + 1

• Adding constant zero can be used to clear the carry flag.

3.4.12.  SUBI: Unsigned Subtract Immediate

• SUBI R_d,R_a,I

• a ≤ 7

• d ≤ 7

• I ≤ 7

• R_d ← R_a - I

• carry ← ( I > R_a ) ? 1 : 0

• PC ← PC + 1

3.4.13.  ASRI: Arithmetic Shift Right Immediate

• ASRI R_d,R_a,I

• a ≤ 7

• d ≤ 7

• 1 ≤ I ≤ 8

• R_d ← ( R_a | ( carry << 16 ) ) >> I )

• carry ← 0

• PC ← PC + 1

• The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 000₂. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).

3.4.14.  LSLI: Logical Shift Left Immediate

• LSLI R_d,R_a,I

• a ≤ 7

• d ≤ 7

• 1 ≤ I ≤ 8

• R_d ← R_a << I

• PC ← PC + 1

• The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 000₂. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).

3.4.15.  LSRI: Logical Shift Right Immediate

• LSRI R_d,R_a,I

• a ≤ 7

• d ≤ 7

• 1 ≤ I ≤ 8

• R_d ← R_a >> I

• PC ← PC + 1

• The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 000₂. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).

3.4.16.  MOVI: Move Immediate to Register

• MOVI R_d,I

• d ≤ 7

• I ≤ 63

• R_d ← I

• PC ← PC + 1

3.5.1.  LDB: Indexed Load Byte

• LDB R_d,(R_a,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← dmem[R_a + SignExt(S)]

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.2.  LDW: Indexed Load Word

• LDW R_d,(R_a,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← dmem [R_a + SignExt(S)] | (dmem[R_a + SignExt(S) + 1] << 8)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.3.  LDB: Indexed Load Byte with Postincrement

• LDB R_d,(R_a+,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← dmem[R_a + SignExt(S)]

• R_a ← R_a + SignExt(S)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.4.  LDW: Indexed Load Word with Postincrement

• LDW R_d,(R_a+,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← dmem[R_a + SignExt(S)] | (dmem[R_a + SignExt(S) + 1] << 8)

• R_a ← R_a + SignExt(S)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.5.  LDB: Indexed Load Byte with Predecrement

• LDB R_d,(-R_a,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_a ← R_a - SignExt(S)

• R_d ← dmem[R_a]

• PC ← PC + 1

• For the avoidance of doubt, the decrement of R_a is carried out before R_a is used to compute the address for loading.

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.6.  LDW: Indexed Load Word with Predecrement

• LDW R_d,(-R_a,S)

• d ≤ 7

• -4 ≤ S ≤ 3

• R_a ← R_a - SignExt(S)

• R_d ← dmem[R_a] | (dmem[R_a + 1] << 8)

• PC ← PC + 1

• For the avoidance of doubt, the decrement of R_a is carried out before R_a is used to compute the address for loading.

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.7.  STB: Indexed Store Byte

• STB (R_d,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• dmem[R_d + SignExt(S)] ← (R_a & 255)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.8.  STW: Indexed Store Word

• STW (R_d,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• dmem[R_d + SignExt(S)] ← (R_a & 255)

• dmem[R_d + SignExt(S) + 1] ← (R_a >> 8)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.9.  STB: Indexed Store Byte with Postincrement

• STB (R_d+,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• dmem[R_d + SignExt(S)] ← (R_a & 255)

• R_d ← R_d + SignExt(S)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.10.  STW: Indexed Store Word with Postincrement

• STW (R_d+,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• dmem[R_d + SignExt(S)] ← (R_a & 255)

• dmem[R_d + SignExt(S) + 1] ← (R_a >> 8)

• R_d ← R_d + SignExt(S)

• PC ← PC + 1

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.11.  STB: Indexed Store Byte with Predecrement

• STB (-R_d,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← R_d - SignExt(S)

• dmem[R_d] ← (R_a & 255)

• PC ← PC + 1

• For the avoidance of doubt, the decrement of R_a is carried out before R_a is used to compute the address for loading.

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.5.12.  STW: Indexed Store Word with Predecrement

• STW (-R_d,S),R_a

• d ≤ 7

• -4 ≤ S ≤ 3

• R_d ← R_d - SignExt(S)

• dmem[R_d] ← (R_a & 255)

• dmem[R_d + 1] ← (R_a >> 8)

• PC ← PC + 1

• For the avoidance of doubt, the decrement of R_a is carried out before R_a is used to compute the address for loading.

• This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.

3.6.1.  BRA: Relative Branch

• BRA S

• -256 ≤ S ≤ 255

• PC ← PC + SignExt(S)

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.2.  BAL: Relative Branch and Link

• BAL S,R_b

• b ≤ 7

• -32 ≤ S ≤ 31

• R_b ← PC + 1

• PC ← PC + SignExt(S)

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.3.  BEQ: Relative Branch if Equal

• BEQ S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a = R_b) ? PC + SignExt(S) : PC + 1

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.4.  BNE: Relative Branch if Not Equal

• BNE S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a ≠ R_b) ? PC + SignExt(S) : PC + 1

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.5.  BLTS: Relative Branch if Signed Less Than

• BLTS S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a < R_b) ? PC + SignExt(S) : PC + 1

• The comparison between R_a and R_b is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.6.  BLES: Relative Branch if Signed Less Than or Equal To

• BLES S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a ≤ R_b) ? PC + SignExt(S) : PC + 1

• The comparison between R_a and R_b is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.7.  BLTU: Relative Branch if Unsigned Less Than

• BLTU S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a < R_b) ? PC + SignExt(S) : PC + 1

• The comparison between R_a and R_b is an unsigned comparison.

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.8.  BLEU: Relative Branch if Unsigned Less Than or Equal To

• BLEU S,R_a,R_b

• a ≤ 7

• b ≤ 7

• -4 ≤ S ≤ 3

• PC ← (R_a ≤ R_b) ? PC + SignExt(S) : PC + 1

• The comparison between R_a and R_b is an unsigned comparison.

• Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.

• Branching to a non-existent location will trigger a bus error exception.

3.6.9.  JMP: Absolute Jump

• JMP R_d

• d ≤ 7

• PC ← R_d

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jumping to a non-existent location will trigger a bus error exception.

3.6.10.  JAL: Absolute Jump and Link

• JAL R_d,R_b

• b ≤ 7

• d ≤ 7

• R_b ← PC + 1

• PC ← R_d

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jumping to a non-existent location will trigger a bus error exception.

3.6.11.  JEQ: Absolute Jump if Equal

• JEQ R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a = R_b) ? R_d : PC + 1

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.6.12.  JNE: Absolute Jump if Not Equal

• JNE R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a ≠ R_b) ? R_d : PC + 1

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.6.13.  JLTS: Absolute Jump if Signed Less Than

• JLTS R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a < R_b) ? R_d : PC + 1

• The comparison between R_a and R_b is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.6.14.  JLES: Absolute Jump if Signed Less Than or Equal To

• JLES R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a ≤ R_b) ? R_d : PC + 1

• The comparison between R_a and R_b is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.6.15.  JLTU: Absolute Jump if Unsigned Less Than

• JLTU R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a < R_b) ? R_d : PC + 1

• The comparison between R_a and R_b is an unsigned comparison.

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.6.16.  JLEU: Absolute Jump if Unsigned Less Than or Equal To

• JLEU R_d,R_a,R_b

• a ≤ 7

• b ≤ 7

• d ≤ 7

• PC ← (R_a ≤ R_b) ? R_d : PC + 1

• The comparison between R_a and R_b is an unsigned comparison.

• Remember that the program counter is a word address, so the value in R_d should be a word address.

• Jump to a non-existent location will trigger a bus error exception.

3.7.1.  RTE: Return from Exception

• RTE R_d

• d ≤ 7

• PC ← R_d

• This opcode is not fully defined, pending agreement on the exception mechanism for AAP.

3.8.1.  NOP: No Operation

• NOP R_d,I

• d ≤ 63

• I ≤ 4095

• PC ← PC + 1

• This opcode may trigger side-effects in implementations, depending on the value of I, particularly when simulating (see Section 2.3).

• There are no conventions for any values of d or I for the 32-bit version of NOP.

3.8.2.  ADD: Unsigned Add

• ADD R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a + R_b

  carry ← ( ( R_a + R_b ) ≥ 2¹⁶ ) ? 1 : 0

  PC ← PC + 2

3.8.3.  SUB: Unsigned Subtract

• SUB R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a - R_b

• carry ← ( R_b > R_a ) ? 1 : 0

• PC ← PC + 2

3.8.4.  AND: Bitwise AND

• AND R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a & R_b

• PC ← PC + 2

3.8.5.  OR: Bitwise OR

• OR R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a | R_b

• PC ← PC + 2

3.8.6.  XOR: Bitwise Exclusive OR

• XOR R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a ^ R_b

• PC ← PC + 2

3.8.7.  ASR: Arithmetic Shift Right

• ASR R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← ( R_a | ( carry << 16 ) ) >> R_b )

• carry ← 0

• PC ← PC + 2

• If R_b ≥ 17 the result in R_d will be zero.

• The carry flag is always cleared, even if a shift of zero is specified.

3.8.8.  LSL: Logical Shift Left

• LSL R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a << R_b

• PC ← PC + 2

• If R_b ≥ 16 the result in R_d will be zero.

3.8.9.  LSR: Logical Shift Right

• LSR R_d,R_a,R_b

• a ≤ 63

• b ≤ 63

• d ≤ 63

• R_d ← R_a >> R_b

• PC ← PC + 2

• If R_b ≥ 16 the result in R_d will be zero.

3.8.10.  MOV: Move Register to Register

• MOV R_d,R_a

• a ≤ 63

• d ≤ 63

• R_d ← R_a

• PC ← PC + 2

3.8.11.  ADDI: Unsigned Add Immediate

• ADDI R_d,R_a,I

• a ≤ 63

• d ≤ 63

• I ≤ 63

• R_d ← R_a + I

  carry ← ( ( R_a + I ) ≥ 2¹⁶ ) ? 1 : 0

  PC ← PC + 2

• Adding constant zero can be used to clear the carry flag.

3.8.12.  SUBI: Unsigned Subtract Immediate

• SUBI R_d,R_a,I

• a ≤ 63

• d ≤ 63

• I ≤ 63

• R_d ← R_a - I

• carry ← ( I > R_a ) ? 1 : 0

• PC ← PC + 2

3.8.13.  ASRI: Arithmetic Shift Right Immediate

• ASRI R_d,R_a,I

• a ≤ 63

• d ≤ 63

• 1 ≤ I ≤ 64

• R_d ← ( R_a | ( carry << 16 ) ) >> I )

• carry ← 0

• PC ← PC + 2

• If I ≥ 17 the result in R_d will be zero.

• The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 000000₂. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).

3.8.14.  LSLI: Logical Shift Left Immediate