Fets and Crosses: Tic-Tac-Toe built from 2458 discrete transistors
schilk.coA Work of art. I remember my dad building a computer using discrete TTL chips in our garage in Auckland. He took like two years and I'm guessing about five people saw it. I would love to see more of these on HN, but most don't get past a few upvotes in the sea of AI stuff.
Good news is there's still a lot of that on YouTube. I attribute it to Ben Eater but I'm sure there are others who helped or came before
vaguely related: MENACE
https://en.wikipedia.org/wiki/Matchbox_Educable_Noughts_and_...
Ah, so that's where Fred Saberhagen got the gimmick for his first Berserker story - "Without a Thought" / "Fortress Ship", 1963.
(A spaceman uses a pet that plays with beads to simulate not being temporarily incapacitated by a 'mind beam' attack.)
Thank you.
"A Tinkertoy computer that plays tic-tac-toe" - https://tcm.computerhistory.org/Timeline/TinkerToy.pdf and https://www.computerhistory.org/collections/catalog/X39.81
"Great Tinkertoy Computer" - https://www.science20.com/brain_candyfeed_your_mind/great_ti...
Sweet. About the same number of transistors used in the Intel 4004.
Brilliant to get this done all the way through.
Once you introduce a HDL and start optimizing, I would expect more than half of the transistors to be redundant. But you would end up with a circuit that you will not understand any more.. But that could give an important lesson in chip design and HDL compilers.
UX could use a delay before the next move.
Would standard HDL synthesis engines be better at this in terms of schematic capture? They could do optimizations that I think if I'm reading right weren't done here
What for?
Well stuff like if in one block you invert a signal, and later you invert it again, those optimization engines can cancel that out. Possibly they could also do to fanciness with complicated logical operations to reduce transistor count too. But I'm not entirely sure if their same benefit on FPGA applies to transistors
That's a lot of transistors. Why do I feel it could be done in less? This is the absolute minimum number of Discrete transistors you need?
"In case it is not already obvious, efficiency and sensibility were not a top priority when working on this project. I am sure there are more efficient flip- flop designs or implementations with fewer transistors, especially by building composite gates that combine NAND and NOR gates, but I don't really care :)"
Hats off to you for just saying "no" to optimizations.
I'd have gone down an optimization rabbit hole, while never finishing the original project.