Open-Source RISC-V: Energy Efficiency of Superscalar, Out-of-Order Execution

arxiv.org

108 points by PaulHoule 15 days ago


dkjaudyeqooe - 15 days ago

I feel like an open source RV CPU is very likely in the high-performance space.

The amount of effort required to design and implement such a device makes it difficult for a single company to invest in, but many interested users of it could band together to create a viable open source implementation.

I guess it's a question of a project that such an effort can crystalize around.

fithisux - 14 days ago

RISC-V needs also an open ecosystem to succeed. Open boards, with fully documented chips.

Maybe it will be a very positive step if the CPU/GPU/DSP fused cores materialize.

Pet_Ant - 15 days ago

> some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools

Isn't translating between languages something that LLMs should excel at? I mean I'm sure it's more than just pasting it into ChatGPT but if the design has been validated and it's understood, validating the translated version should be several orders of magnitude easier than starting from scratch.

sylware - 14 days ago

Anybody with deep knowledge of current RISC-V opensource implementations here?

Do harts have store queue and load queue optimizations? Namely some kind of memory request fusion?

I asked this question because since I am writing rv64 assembly, and since rv64 is a load/store architecture, I tend to pack as much as I can memory ordered loads and stores.